公开(公告)号：US10153027B1

公开(公告)日：2018-12-11

申请号：US16106617

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: H01L27/118 ,  G11C11/402 ,  G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US10083734B1

公开(公告)日：2018-09-25

申请号：US15804981

申请日：2017-11-06

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/24 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06

CPC classification number: G11C11/4023 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/4097 ,  G11C2207/105 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10855 ,  H01L27/10885

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US09881910B2

公开(公告)日：2018-01-30

申请号：US15490660

申请日：2017-04-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michel Koopmans

IPC: H01L21/68 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/14 ,  H01L24/80 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68354 ,  H01L2221/68395 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/95001

Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.

公开(公告)号：US20190172517A1

公开(公告)日：2019-06-06

申请号：US16267087

申请日：2019-02-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/402 ,  G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US20190072608A1

公开(公告)日：2019-03-07

申请号：US16177917

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2887 ,  G01R1/07307 ,  G01R31/2884

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

公开(公告)号：US20180108645A1

公开(公告)日：2018-04-19

申请号：US15847493

申请日：2017-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michel Koopmans

IPC: H01L25/00 ,  H01L21/683 ,  H01L23/00 ,  H01L25/18 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/14 ,  H01L24/80 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68354 ,  H01L2221/68395 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/95001

Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.

公开(公告)号：US20150170991A1

公开(公告)日：2015-06-18

申请号：US14105940

申请日：2013-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jian Li ,  Steven K. Groothuis ,  Michel Koopmans

IPC: H01L23/373 ,  H01L25/065

CPC classification number: H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16257 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Abstract translation: 本文公开了具有热隔离件和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括限定空腔的导热壳体，腔内的第一半导体管芯的堆叠，以及相对于第一管芯堆叠堆叠并由封装衬底承载的第二半导体管芯。 半导体管芯组件还包括设置在封装衬底和导热壳体之间的热隔离件。 热隔离物可以包括半导体衬底和延伸穿过半导体衬底并且电耦合到第一半导体管芯，第二半导体管芯和封装衬底的堆叠的多个导电通孔。

公开(公告)号：US20150132869A1

公开(公告)日：2015-05-14

申请号：US14600976

申请日：2015-01-20

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L25/00 ,  H01L21/66 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2224/16145 ,  H01L2224/80203 ,  H01L2224/80815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Abstract translation: 制造多模组件的方法，其包括具有较小横向尺寸的半导体芯片的外围封装的叠层的基底半导体模具，所述芯片由芯片，所得组件和包括这种组件的半导体器件之间的导电元件垂直连接。

公开(公告)号：US20240347511A1

公开(公告)日：2024-10-17

申请号：US18751061

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US12033980B2

公开(公告)日：2024-07-09

申请号：US16871443

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2224/141 ,  H01L2924/00012

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.