公开(公告)号：US09922704B2

公开(公告)日：2018-03-20

申请号：US15189178

申请日：2016-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427

Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.

公开(公告)号：US20170075613A1

公开(公告)日：2017-03-16

申请号：US15342287

申请日：2016-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G06F12/0846

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract translation: 在存储器装置中，标志存储单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

公开(公告)号：US09484101B2

公开(公告)日：2016-11-01

申请号：US14822083

申请日：2015-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Pranav Kalavade ,  Akira Goda ,  Tommaso Vali ,  Violante Moschiano

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459

Abstract: Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of memory cells, determining an upper limit of a resulting threshold voltage distribution for the group of memory cells following a particular programming pulse of the first plurality of programming pulses, and applying a second plurality of programming pulses to the group of memory cells to program second data to the group of memory cells, wherein a characteristic of at least one of the programming pulses of the second plurality of programming pulses is at least partially based on the determined upper limit of the threshold voltage distribution. Methods of programming memories further include programming information indicative of usage of memory cells of a page of memory cells to the page of memory cells during a portion of a programming operation.

Abstract translation: 编程存储器的方法包括将第一多个编程脉冲施加到存储器单元组以将第一数据编程到存储器单元组，确定特定编程脉冲之后的存储器单元组的结果阈值电压分布的上限 的第一多个编程脉冲，并且将第二多个编程脉冲施加到该组存储器单元以将第二数据编程到该组存储器单元，其中第二组编程脉冲中的至少一个编程脉冲的特性 脉冲至少部分地基于所确定的阈值电压分布的上限。 编程存储器的方法还包括在编程操作的一部分期间指示存储器单元的页面的存储器单元的使用的编程信息到存储器单元的页面。

公开(公告)号：US09105337B2

公开(公告)日：2015-08-11

申请号：US14199304

申请日：2014-03-06

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Akira Goda ,  Tommaso Vali ,  Violante Moschiano

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459

Abstract: Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.

Abstract translation: 公开了用于调整存储器上部页面编程的装置和方法。 在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

公开(公告)号：US20130215680A1

公开(公告)日：2013-08-22

申请号：US13854549

申请日：2013-04-01

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Krisha K. Parat ,  Paul D. Ruby

IPC: G11C16/12 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

Abstract translation: 公开了装置，方法和系统，包括使用自动选择性慢程序融合（ASSPC）来提高编程电压分配宽度的装置，方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压（Vt）是否已经达到特定的预编程验证电压。 响应于该确定，施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加，直到单元被适当地编程为止。 还描述了另外的实施例。

公开(公告)号：US20190258404A1

公开(公告)日：2019-08-22

申请号：US16401089

申请日：2019-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US10126967B2

公开(公告)日：2018-11-13

申请号：US15342287

申请日：2016-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

公开(公告)号：US20180190347A1

公开(公告)日：2018-07-05

申请号：US15907826

申请日：2018-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427

Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.

公开(公告)号：US09910594B2

公开(公告)日：2018-03-06

申请号：US14933874

申请日：2015-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20150380091A1

公开(公告)日：2015-12-31

申请号：US14822083

申请日：2015-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Pranav Kalavade ,  Akira Goda ,  Tommaso Vali ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459

Abstract: Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of memory cells, determining an upper limit of a resulting threshold voltage distribution for the group of memory cells following a particular programming pulse of the first plurality of programming pulses, and applying a second plurality of programming pulses to the group of memory cells to program second data to the group of memory cells, wherein a characteristic of at least one of the programming pulses of the second plurality of programming pulses is at least partially based on the determined upper limit of the threshold voltage distribution. Methods of programming memories further include programming information indicative of usage of memory cells of a page of memory cells to the page of memory cells during a portion of a programming operation.

Abstract translation: 编程存储器的方法包括将第一多个编程脉冲施加到存储器单元组以将第一数据编程到存储器单元组，确定特定编程脉冲之后的存储器单元组的结果阈值电压分布的上限 的第一多个编程脉冲，并且将第二多个编程脉冲施加到该组存储器单元以将第二数据编程到该组存储器单元，其中第二组编程脉冲中的至少一个编程脉冲的特性 脉冲至少部分地基于所确定的阈值电压分布的上限。 编程存储器的方法还包括在编程操作的一部分期间指示存储器单元的页面的存储器单元的使用的编程信息到存储器单元的页面。