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    Reduced pitch memory subsystem for memory device
    12.
    发明授权
    Reduced pitch memory subsystem for memory device 有权

    公开(公告)号：US11973031B2

    公开(公告)日：2024-04-30

    申请号：US18083445

    申请日：2022-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

    IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

    CPC classification number: H01L23/528 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827 ,  H10B10/12

    Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

    REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICE
    13.
    发明申请
    REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICE 有权

    公开(公告)号：US20230123487A1

    公开(公告)日：2023-04-20

    申请号：US18083445

    申请日：2022-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

    IPC: H01L23/528 ,  H01L29/78 ,  H10B10/00 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

    Reduced pitch memory subsystem for memory device
    16.
    发明授权
    Reduced pitch memory subsystem for memory device 有权

    公开(公告)号：US11557537B2

    公开(公告)日：2023-01-17

    申请号：US16986776

    申请日：2020-08-06

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

    IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/11 ,  H01L29/66

    Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

    METHODS OF FORMING CAPACITOR STRUCTURES
    17.
    发明申请
    METHODS OF FORMING CAPACITOR STRUCTURES 有权

    公开(公告)号：US20210320099A1

    公开(公告)日：2021-10-14

    申请号：US17358251

    申请日：2021-06-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vladimir Mikhalev ,  Michael Violette

    IPC: H01L27/02 ,  H01L49/02 ,  H01L29/866 ,  H01L27/11526 ,  H01L29/45 ,  G11C16/30 ,  H01L27/11578 ,  H01L27/11551 ,  G11C16/04 ,  H01L27/11573 ,  H01L23/60 ,  H01L23/62 ,  G11C7/24

    Abstract: Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

    METHODS OF FORMING INTEGRATED CIRCUIT WELL STRUCTURES
    18.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT WELL STRUCTURES 审中-公开

    公开(公告)号：US20190206688A1

    公开(公告)日：2019-07-04

    申请号：US15892584

    申请日：2018-02-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Michael Violette ,  Vladimir Mikhalev

    IPC: H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66

    Abstract: Methods of forming a portion of an integrated circuit include forming a patterned mask having an opening and exposing a surface of a semiconductor material, forming a first doped region at a first level of the semiconductor material through the opening, and isotropically removing a portion of the patterned mask to increase a width of the opening. The methods further include forming a second doped region at a second level of the semiconductor region through the opening after isotropically removing the portion of the patterned mask, wherein the second level is closer to the surface of the semiconductor material than the first level.

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