公开(公告)号：US20150179514A1

公开(公告)日：2015-06-25

申请号：US14138038

申请日：2013-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Hsu-Sheng Yu ,  Hong-Ji Lee ,  N.T. Lian ,  T.H. Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/67 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/67207 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cluster tool is disclosed that can increase throughput of a wafer fabrication process by facilitating removal of barrier overhang in contact holes of contact film stacks. Individual chambers of the cluster tool provide for deposition of barrier material onto a semiconductor structure, depositing over with an amorphous carbon film (ACF), etching back the ACF, and etching a corner region of the contact hole. Removal of the barrier overhang improves the quality of metal fill-in of the contact hole. An expectedly ensuing feature entails a technique in which filling-in of the contact hole with a metal such as tungsten can be achieved with attenuated or eliminated adverse consequence.

Abstract translation: 公开了一种集群工具，其可以通过有助于去除接触膜堆叠的接触孔中的阻挡突出部来增加晶片制造工艺的生产量。 集群工具的单个室提供阻挡材料沉积到半导体结构上，用无定形碳膜（ACF）沉积，对ACF进行蚀刻，并蚀刻接触孔的拐角区域。 阻挡突出部的移除提高了接触孔的金属填充质量。 预期的随后特征需要一种技术，其中可以通过减弱或消除不利后果来实现用诸如钨的金属填充接触孔。

公开(公告)号：US09012282B2

公开(公告)日：2015-04-21

申请号：US13942490

申请日：2013-07-15

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L23/48 ,  H01L29/40 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract translation: 公开了一种制备用于形成硅化物的半导体栅极的自对准方法，例如硅化钴（CoSi）层。 氮化硅（SiN）和低温氧化物（LTO）衬垫类型的沉积，具有突出结构的SiN衬垫防止在形成自对准源时损坏栅极。 未损坏的栅极适用于CoSi沉积。

公开(公告)号：US20220399361A1

公开(公告)日：2022-12-15

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US10424593B2

公开(公告)日：2019-09-24

申请号：US15866132

申请日：2018-01-09

Applicant: MACRONIX International Co., Ltd.

Inventor： I-Ting Lin ,  Yuan-Chieh Chiu ,  Hong-Ji Lee

IPC: H01L27/11578 ,  G11C14/00 ,  G11C16/04 ,  H01L21/28 ,  H01L27/1157 ,  G11C16/34 ,  G11C11/56

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

公开(公告)号：US20180211921A1

公开(公告)日：2018-07-26

申请号：US15415699

申请日：2017-01-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Min-Hsuan Huang

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/32139 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53295

Abstract: An interconnect structure including a substrate and a conductive pattern is provided. The conductive pattern includes a bottom portion. The bottom portion of the conductive pattern is disposed on the substrate. The conductive pattern has a notch on each of two sidewalls of the bottom portion.

公开(公告)号：US09922876B1

公开(公告)日：2018-03-20

申请号：US15414386

申请日：2017-01-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Min-Hsuan Huang

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53266

Abstract: An interconnect structure including a substrate, a dielectric layer, a first conductive pattern, and a second conductive pattern is provided. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.

公开(公告)号：US09449915B2

公开(公告)日：2016-09-20

申请号：US14582935

申请日：2014-12-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Hsu-Sheng Yu

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L23/5226 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a dielectric layer. The dielectric layer is located on the substrate. The dielectric layer has a plurality of openings, and side walls of the openings have concave-and-convex profile.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括衬底和电介质层。 电介质层位于衬底上。 电介质层具有多个开口，开口的侧壁具有凹凸形状。

公开(公告)号：US09425086B2

公开(公告)日：2016-08-23

申请号：US14138007

申请日：2013-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hsu-Sheng Yu ,  Kuo-Feng Lo ,  Hong-Ji Lee

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.

Abstract translation: 描述了形成在接触膜叠层中的接触孔中消除悬垂的方法。 衬垫层覆盖在接触膜叠层上，衬垫也涂覆接触孔。 衬里的一部分被去除以露出突出端，并且去除暴露的突出端。 衬套也用于填充接触孔的弯曲轮廓，从而使接触孔的侧壁平滑和直线适于金属填充，同时抑制管道缺陷。

公开(公告)号：US20160064479A1

公开(公告)日：2016-03-03

申请号：US14468832

申请日：2014-08-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first dielectric layer, a first conductive layer, and an isolation structure. The substrate has a trench. The first dielectric layer is disposed on the substrate between two neighboring trenches. The first conductive layer is disposed on the first dielectric layer. The isolation structure, including a step zone and a recessed zone, is disposed in the trench, wherein an upper surface of the step zone is higher than an upper surface of the first dielectric layer.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括衬底，第一介电层，第一导电层和隔离结构。 衬底具有沟槽。 第一电介质层设置在两个相邻沟槽之间的衬底上。 第一导电层设置在第一介电层上。 包括阶梯区和凹陷区的隔离结构设置在沟槽中，其中台阶区的上表面高于第一介电层的上表面。

公开(公告)号：US09224803B2

公开(公告)日：2015-12-29

申请号：US13875998

申请日：2013-05-02

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L23/58 ,  H01L29/06 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L29/06 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract translation: 通过使用其中形成有沟槽的阻挡层形成具有大纵横比的小接触孔。 在沟槽上方形成较大的接触孔，并利用沟槽和阻挡层的特性形成小沟槽下方的小接触孔，以限制小接触孔的尺寸。