公开(公告)号：US09368220B2

公开(公告)日：2016-06-14

申请号：US14451166

申请日：2014-08-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

IPC: G11C16/16 ,  G11C16/14 ,  G11C29/34 ,  G11C16/04 ,  G11C29/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/14 ,  G11C29/34 ,  G11C2029/2602

Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

Abstract translation: 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

公开(公告)号：US09147501B2

公开(公告)日：2015-09-29

申请号：US13903574

申请日：2013-05-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC: G11C29/00 ,  G11C29/12 ,  G11C16/34

CPC classification number: G11C16/34 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50004 ,  G11C29/50016

Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

Abstract translation: 集成电路存储器件包括非易失性电荷捕获存储器单元的阵列，其被配置为使用阈值状态将数据值存储在阵列中的存储器单元中，所述阈值状态包括以超过所选择的读偏差的最小阈值为特征的较高阈值状态。 控制器包括待机模式，写入模式和读取模式。 保持检查逻辑在上电或待机模式下执行，以识别在阈值保持检查失败的较高阈值状态下的存储器单元。 此外，提供逻辑以重新编程所识别的存储器单元。

公开(公告)号：US09123390B2

公开(公告)日：2015-09-01

申请号：US14183315

申请日：2014-02-18

Applicant: Macronix International Co., Ltd.

Inventor： Nai-Ping Kuo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Ming-Chih Hsieh

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/00 ,  G11C7/10 ,  G11C7/20

Abstract: In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code.

Abstract translation: 在所公开的技术中，存储器集成电路的器件识别码是可变的。 在一些情况下，多个设备识别码存储在存储器集成电路上，并且多个设备识别码选择数据被存储在存储器集成电路上。 设备识别码寄存器可以存储所选择的设备标识码。

公开(公告)号：US20150023120A1

公开(公告)日：2015-01-22

申请号：US14506768

申请日：2014-10-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

Abstract translation: 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线组保持预充电。

公开(公告)号：US20140219026A1

公开(公告)日：2014-08-07

申请号：US14249270

申请日：2014-04-09

Applicant: Macronix International Co., Ltd.

Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC: G11C16/34

CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

公开(公告)号：US12198770B2

公开(公告)日：2025-01-14

申请号：US17988773

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Chen-Huan Chen ,  Ken-Hui Chen

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

公开(公告)号：US12197745B2

公开(公告)日：2025-01-14

申请号：US17817711

申请日：2022-08-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F3/06

Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

公开(公告)号：US20230377633A1

公开(公告)日：2023-11-23

申请号：US17751445

申请日：2022-05-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Shang-Chi Yang ,  Fu-Nian Liang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/06

CPC classification number: G11C11/4094 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/063

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

公开(公告)号：US11258599B2

公开(公告)日：2022-02-22

申请号：US16793986

申请日：2020-02-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Chen-Chia Fan

IPC: H04L9/08 ,  H04L9/32 ,  G06F21/62 ,  G06F3/06 ,  G06F12/0877

Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.

公开(公告)号：US10809925B2

公开(公告)日：2020-10-20

申请号：US16259268

申请日：2019-01-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Chin-Hung Chang ,  Yu-Chen Wang

IPC: G06F3/06 ,  G06F12/14

Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.