公开(公告)号：US11037632B1

公开(公告)日：2021-06-15

申请号：US16828997

申请日：2020-03-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Chih-Chieh Cheng ,  Cheng-Hsien Cheng ,  Yu-Hung Huang ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.

公开(公告)号：US09620603B2

公开(公告)日：2017-04-11

申请号：US14694325

申请日：2015-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Chih-Hsiung Lee

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L29/4916

Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a p-n junction in a conductive layer. The method may allow for the production of semiconductor memory devices of reduced size.

公开(公告)号：US20160372202A1

公开(公告)日：2016-12-22

申请号：US14742054

申请日：2015-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

Abstract translation: 本文中设想的方法和装置用于增强非易失性存储器件的程序性能。 在示例实施例中，非易失性存储器件包括包括多个层的非易失性存储器单元的3D阵列，每个层包括非易失性存储器单元的NAND串，耦合到位线的NAND串和多个SSL和字线， 所述SSL和所述字线与所述NAND串正交排列，所述字线在所述多个NAND串的表面和所述字线之间的交叉点处建立所述非易失性存储单元，所述NAND串中的每一个还包括多个SSL晶体管 将SSL耦合到NAND串，其中至少第一SSL被配置为接收第一电压，第二SSL被配置为在第二电压下接收，并且其中第二SSL更靠近字线。

公开(公告)号：US08859364B2

公开(公告)日：2014-10-14

申请号：US14153897

申请日：2014-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Shaw-Hung Ku ,  Chi-Pei Lu ,  Chun-Lien Su

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract translation: 本发明提供了一种非易失性存储器的制造方法，包括在衬底上形成栅介质层; 在栅介质层上形成浮栅; 在浮栅上形成第一电荷阻挡层; 在所述第一电荷阻挡层上形成氮化物层; 在所述氮化物层上形成第二电荷阻挡层; 在所述第二电荷阻挡层上形成控制栅极; 并对氮化物层进行处理以获得更高的介电常数。

公开(公告)号：US11361824B1

公开(公告)日：2022-06-14

申请号：US17164976

申请日：2021-02-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Cheng-Hsien Cheng ,  Chun-Chang Lu ,  Wen-Jer Tsai

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

Abstract: Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.

公开(公告)号：US20210305273A1

公开(公告)日：2021-09-30

申请号：US16835360

申请日：2020-03-31

Applicant: MACRONIX International Co., Ltd.

Inventor： CHIH-HSIUNG LEE ,  Shaw-Hung Ku

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.

公开(公告)号：US10796753B1

公开(公告)日：2020-10-06

申请号：US16667653

申请日：2019-10-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Yin-Jen Chen

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour. The shrinkage-quantity topographic contour and the program-shot-number topographic contour are overlapped to determine an operation region formed from an application range of the bit line voltage and an application range of the voltage difference value.

公开(公告)号：US20190080750A1

公开(公告)日：2019-03-14

申请号：US15698812

申请日：2017-09-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Ta-Wei Lin ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Wen-Jer Tsai

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

公开(公告)号：US09859007B2

公开(公告)日：2018-01-02

申请号：US14742054

申请日：2015-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

公开(公告)号：US09589982B1

公开(公告)日：2017-03-07

申请号：US14854383

申请日：2015-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.

Abstract translation: 本发明的实施例提供改进的三维存储器单元，阵列，器件和/或类似物以及相关联的方法。 在一个实施例中，提供三维存储单元。 三维存储单元包括第一导电层; 与所述第一导电层间隔开的第三导电层; 连接第一导电层和第三导电层以形成具有内表面的开口的沟道导电层; 沿着由所述第一导电层，所述沟道导电层和所述第三导电层包围的所述开口的内表面设置的电介质层; 以及插入并基本上填充由电介质层形成的剩余开口部分的第二导电层。 第一导电层，电介质层和第二导电层被配置成形成阶梯结构。