公开(公告)号：US11018154B2

公开(公告)日：2021-05-25

申请号：US16543688

申请日：2019-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Chang Lu ,  Wen-Jer Tsai ,  Guan-Wei Wu ,  Yao-Wen Chang

IPC: H01L27/11582 ,  H01L29/36 ,  H01L29/10 ,  H01L23/528 ,  H01L21/265 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

公开(公告)号：US10763273B2

公开(公告)日：2020-09-01

申请号：US16110897

申请日：2018-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11565 ,  G11C16/26

Abstract: A memory device comprises an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor. The array comprises a plurality of stacks of conductive lines, a stack of conductive lines including a select gate line and a word line adjacent the select gate line. The device comprises an array of vertical channel lines disposed through the conductive lines to a reference line, gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors in the array of vertical channel lines and the select gate lines, charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors in the array of vertical channel lines and the word lines, and bit lines coupled to the vertical channel lines via upper ends of the vertical channel lines.

公开(公告)号：US20200066741A1

公开(公告)日：2020-02-27

申请号：US16110897

申请日：2018-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14

Abstract: A memory device comprises an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor. The array comprises a plurality of stacks of conductive lines, a stack of conductive lines including a select gate line and a word line adjacent the select gate line. The device comprises an array of vertical channel lines disposed through the conductive lines to a reference line, gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors in the array of vertical channel lines and the select gate lines, charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors in the array of vertical channel lines and the word lines, and bit lines coupled to the vertical channel lines via upper ends of the vertical channel lines.

公开(公告)号：US09978457B1

公开(公告)日：2018-05-22

申请号：US15358300

申请日：2016-11-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  I-Chen Yang

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3422

Abstract: A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias and the third bias are different.

公开(公告)号：US20180137918A1

公开(公告)日：2018-05-17

申请号：US15350157

申请日：2016-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42392

Abstract: “A method for operating a memory array includes an all programming step, an erasing step and a selectively programming step. The all programming step is to program all of memory cells of a NAND string. The erasing step is to erase the all of the memory cells of the string after the all programming step. The selectively programming step is to program a portion of the all of memory cells of the NAND string after the erasing step. The NAND string includes a pillar channel layer, a pillar memory layer and control gates. The pillar memory layer is surrounded by the control gates separated from each other. The memory cells are defined at intersections of the pillar channel layer and the control gates.”

公开(公告)号：US09858995B1

公开(公告)日：2018-01-02

申请号：US15387792

申请日：2016-12-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tao-Yuan Lin ,  I-Chen Yang ,  Yao-Wen Chang

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: A memory device includes N word lines, wherein the word lines include an ith word line coupled to an ith memory cell and an (i+1)th word line coupled to an (i+1)th memory cell which is disposed adjacent to the ith memory cell and is a programmed memory cell, and i is an integer from 0 to (N−2). A method of operating such a memory device method includes a reading step. In the reading step, a read voltage is provided to the ith word line, a first pass voltage is provided to the (i+1)th word line, and a second pass voltage is provided to the others of the word lines, wherein the second pass voltage is lower than the first pass voltage.

公开(公告)号：US09509137B2

公开(公告)日：2016-11-29

申请号：US14272115

申请日：2014-05-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Yu Wang ,  Tao-Cheng Lu ,  Yao-Wen Chang

IPC: H02H3/20 ,  H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0259

Abstract: An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.

Abstract translation: 提供一种包括PNP晶体管，保护电路和调整电路的静电放电保护装置。 PNP晶体管的发射极电连接到焊盘，并且PNP晶体管的集电极电连接到地。 保护电路电连接在PNP晶体管的基极与地之间，并提供放电路径。 当在焊盘上发生静电信号时，静电信号通过放电路径和PNP晶体管传导到地面。 调节电路电连接在PNP晶体管的发射极和基极之间。 当向焊盘提供电源电压时，调节电路根据电源电压向PNP晶体管的基极提供控制电压，以防止PNP晶体管的发射极和基极正向偏置。

公开(公告)号：US09082620B1

公开(公告)日：2015-07-14

申请号：US14150638

申请日：2014-01-08

Applicant: Macronix International Co., Ltd.

Inventor： Shih Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L29/74 ,  H01L31/111 ,  H01L27/02 ,  H01L29/08

CPC classification number: H01L27/0262 ,  H01L27/0266 ,  H01L29/74 ,  H01L29/861

Abstract: A semiconductor device includes a substrate, and first and second wells formed in the substrate. The first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type. The device includes a first heavily-doped region having the first conductivity type and a second heavily-doped region having the first conductivity type. A portion of the first heavily-doped region is formed in the first well. The second heavily-doped region is formed in the second well. The device also includes an insulating layer formed over a channel region of the substrate between the first and second heavily-doped regions, and a gate electrode formed over the insulating layer. The device further includes a terminal for coupling to a circuit being protected, and a switching circuit coupled between the terminal and the first heavily-doped region, and between the terminal and the gate electrode.

Abstract translation: 半导体器件包括衬底以及形成在衬底中的第一阱和第二阱。 第一阱具有第一导电类型。 第二阱具有与第一导电类型不同的第二导电类型。 该器件包括具有第一导电类型的第一重掺杂区和具有第一导电类型的第二重掺杂区。 在第一阱中形成第一重掺杂区的一部分。 在第二阱中形成第二重掺杂区域。 该器件还包括在第一和第二重掺杂区域之间的衬底的沟道区域上形成的绝缘层，以及形成在绝缘层上的栅电极。 该器件还包括用于耦合到被保护的电路的端子，以及耦合在端子和第一重掺杂区域之间以及端子和栅电极之间的开关电路。

公开(公告)号：US20150023098A1

公开(公告)日：2015-01-22

申请号：US13943691

申请日：2013-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/3422

Abstract: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.

Abstract translation: 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。

公开(公告)号：US20250056816A1

公开(公告)日：2025-02-13

申请号：US18780515

申请日：2024-07-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Yung-Hsiang Chen ,  I-Chen Yang ,  Hsing-Wen Chang ,  Yao-Wen Chang

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.