公开(公告)号：US20140252464A1

公开(公告)日：2014-09-11

申请号：US14284808

申请日：2014-05-22

申请人： Bernhard Sell ,  Oleg Golonzka

发明人： Bernhard Sell ,  Oleg Golonzka

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US07943992B2

公开(公告)日：2011-05-17

申请号：US12157556

申请日：2008-06-10

申请人： Bernhard Sell ,  Rishabh Mehandru

发明人： Bernhard Sell ,  Rishabh Mehandru

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621

摘要： Methods and associated structures of forming a microelectronic device are described. Those structures may comprise a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些结构可以包括晶体管，其包括设置在基板上的栅极电介质上的金属栅极和与晶体管的沟道区域相邻设置的源极/漏极区域。 源极/漏极区域包括源极/漏极延伸部分，其包括顶点，其中沟道区域的顶表面与顶点基本上是平面的。

公开(公告)号：US07829943B2

公开(公告)日：2010-11-09

申请号：US12650995

申请日：2009-12-31

申请人： Bernhard Sell

发明人： Bernhard Sell

IPC分类号： H01L29/94

CPC分类号： H01L29/4983 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S257/90

摘要： A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.

公开(公告)号：US20080242037A1

公开(公告)日：2008-10-02

申请号：US11729189

申请日：2007-03-28

申请人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

发明人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

摘要翻译： 一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中 掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域 以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料 基质。

公开(公告)号：US20070238236A1

公开(公告)日：2007-10-11

申请号：US11391928

申请日：2006-03-28

申请人： Ted Cook ,  Bernhard Sell ,  Anand Murthy

发明人： Ted Cook ,  Bernhard Sell ,  Anand Murthy

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method and apparatus to improve the contact formation of salicide and reduce the external resistance of a transistor is disclosed. A gate electrode is formed on a surface of a substrate. A source region and a drain region are isotropically etched in the substrate. A Silicon Germanium alloy is doped in situ with Boron in the source region and in the drain region. Silicon is deposited on the Silicon Germanium alloy. Nickel is deposited on the Silicon. A Nickel Silicon Germanium silicide layer is formed on the Silicon Germanium alloy. A Nickel Silicon silicide layer is formed on the Nickel Silicon Germanium silicide layer.

摘要翻译： 公开了一种改善硅化物的接触形成并降低晶体管的外部电阻的方法和装置。 在基板的表面上形成栅电极。 源极区域和漏极区域在基板中被各向同性地蚀刻。 在源区和漏区中硼原位掺杂硅锗合金。 硅沉积在硅锗合金上。 镍沉积在硅上。 在硅锗合金上形成硅锗硅化硅层。 镍硅化硅层形成在硅锗硅化硅层上。

公开(公告)号：US06960524B2

公开(公告)日：2005-11-01

申请号：US10692150

申请日：2003-10-21

申请人： Thomas Hecht ,  Bernhard Sell ,  Annette Saenger

发明人： Thomas Hecht ,  Bernhard Sell ,  Annette Saenger

IPC分类号： C23C16/02 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28194 ,  C23C16/0272 ,  H01L21/28079 ,  H01L21/28211 ,  H01L21/28518 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/76802 ,  H01L21/76831 ,  H01L28/60 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

摘要： The invention relates to a method for production of a metallic or metal-containing layer (5) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon- or germanium-containing layer before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements or the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.

摘要翻译： 本发明涉及一种通过在含锗层或含锗层上使用前体来制造金属或含金属层（5）的方法，特别是电子元件，由此施加中间层 到使用前的硅或锗含量层。 所述中间层至少形成了用于蚀刻含硅或含锗层的元素或前体的扩散阻挡层，并且本身对前蚀刻的蚀刻本身具有抗蚀性。

公开(公告)号：US20130313610A1

公开(公告)日：2013-11-28

申请号：US13995634

申请日：2011-12-22

申请人： Bernhard Sell

发明人： Bernhard Sell

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/823412 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US20110215375A1

公开(公告)日：2011-09-08

申请号：US13107739

申请日：2011-05-13

申请人： Ted E. Cook, JR. ,  Bernhard Sell ,  Anand Murthy

发明人： Ted E. Cook, JR. ,  Bernhard Sell ,  Anand Murthy

IPC分类号： H01L29/06

CPC分类号： H01L29/7848 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834

摘要： A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

摘要翻译： 描述了多组分应变诱导半导体区域。 在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。 在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。 在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。

公开(公告)号：US20090321942A1

公开(公告)日：2009-12-31

申请号：US12215991

申请日：2008-06-30

申请人： Bernhard Sell ,  Oleg Golonzka

发明人： Bernhard Sell ,  Oleg Golonzka

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US20090321838A1

公开(公告)日：2009-12-31

申请号：US12215989

申请日：2008-06-30

申请人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel B. Aubertine

发明人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel B. Aubertine

IPC分类号： H01L29/423 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/66628 ,  H01L29/7834

摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。 晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134） 绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。 所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。