公开(公告)号：US11967570B2

公开(公告)日：2024-04-23

申请号：US17687350

申请日：2022-03-04

Applicant: MediaTek Inc.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01Q1/02 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/3672 ,  H01L23/3733 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/02 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/18161

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US11908767B2

公开(公告)日：2024-02-20

申请号：US17545015

申请日：2021-12-08

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu ,  Chia-Hao Hsu

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49822

Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

公开(公告)号：US20230039444A1

公开(公告)日：2023-02-09

申请号：US17965787

申请日：2022-10-14

Applicant: MEDIATEK INC.

Inventor： Wen-Chou Wu ,  Yi-Chieh Lin ,  Chia-Yu Jin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/498 ,  H01Q21/06 ,  H01L25/16

Abstract: A semiconductor package includes a first package having a first side and a second side opposing the first side. The first package comprises a first electronic component and a second electronic component arranged in a side-by-side manner on the second side. A second package is mounted on the first side of the first package. The second package comprises a radiative antenna element. A connector is disposed on the second side.

公开(公告)号：US20220285297A1

公开(公告)日：2022-09-08

申请号：US17687350

申请日：2022-03-04

Applicant: MediaTek Inc.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US11302657B2

公开(公告)日：2022-04-12

申请号：US16802576

申请日：2020-02-27

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US20210036405A1

公开(公告)日：2021-02-04

申请号：US17075561

申请日：2020-10-20

Applicant: MediaTek Inc.

Inventor： Fu-Yi Han ,  Che-Ya Chou ,  Che-Hung Kuo ,  Wen-Chou Wu ,  Nan-Cheng Chen ,  Min-Chen Lin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

公开(公告)号：US12165961B2

公开(公告)日：2024-12-10

申请号：US18329721

申请日：2023-06-06

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Zheng Zeng ,  Che-Hung Kuo

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

公开(公告)号：US20230422525A1

公开(公告)日：2023-12-28

申请号：US18203666

申请日：2023-05-31

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H10B12/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H10B12/00 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

公开(公告)号：US11776899B2

公开(公告)日：2023-10-03

申请号：US17179357

申请日：2021-02-18

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu

IPC: H01L23/522 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L23/3114 ,  H01L23/3128

Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

公开(公告)号：US11721882B2

公开(公告)日：2023-08-08

申请号：US17075561

申请日：2020-10-20

Applicant: MediaTek Inc.

Inventor： Fu-Yi Han ,  Che-Ya Chou ,  Che-Hung Kuo ,  Wen-Chou Wu ,  Nan-Cheng Chen ,  Min-Chen Lin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01Q1/2283 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/20 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16141 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19042 ,  H01L2924/19106

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.