公开(公告)号：US20240243046A1

公开(公告)日：2024-07-18

申请号：US18402667

申请日：2024-01-02

Applicant: MEDIATEK INC.

Inventor： Chun-Yin Lin ,  Tai-Yu Chen ,  Li-Song Lin ,  Chi-Yuan Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/49816 ,  H01L23/3735 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351

Abstract: A flip chip ball grid array package includes a package substrate and a flip chip device mounted on a top surface of the package substrate. The flip chip device includes a semiconductor integrated circuit die; an epoxy molding compound encapsulating vertical sidewalls of the semiconductor integrated circuit die; a re-distribution layer structure disposed on an active surface of the semiconductor integrated circuit die and on a lower surface of the epoxy molding compound; a sintered nanosilver layer disposed on a passive rear surface of the semiconductor integrated circuit die and on an upper surface of the epoxy molding compound; and a stiffener ring mounted around the flip chip device on the package substrate.

公开(公告)号：US20230422525A1

公开(公告)日：2023-12-28

申请号：US18203666

申请日：2023-05-31

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H10B12/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H10B12/00 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

公开(公告)号：US20230282625A1

公开(公告)日：2023-09-07

申请号：US18107520

申请日：2023-02-09

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Shih-Chin Lin ,  Tai-Yu Chen ,  Bo-Jiun Yang ,  Bing-Yeh Lin ,  Yung-Cheng Huang ,  Wen-Sung Hsu ,  Bo-Hao Ma ,  Isabella Song

IPC: H01L25/10 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/481 ,  H01L23/49866 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L2224/73204 ,  H01L2224/08112 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/183

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.

公开(公告)号：US11705413B2

公开(公告)日：2023-07-18

申请号：US17549901

申请日：2021-12-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/3672 ,  H01L23/3733 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/02 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/18161

Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US10109608B2

公开(公告)日：2018-10-23

申请号：US15189369

申请日：2016-06-22

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Tai-Yu Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

公开(公告)号：US20180261528A1

公开(公告)日：2018-09-13

申请号：US15863984

申请日：2018-01-08

Applicant: MEDIATEK INC.

Inventor： Tai-Yu Chen ,  Wen-Sung Hsu ,  Sheng-Liang Kuo ,  Chi-Wen Pan ,  Jen-Chuan Chen

IPC: H01L23/433 ,  H01L25/18 ,  H01L23/367

Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, an interposer mounted on the top surface of the package substrate, a first semiconductor die and a second semiconductor die mounted on the interposer in a side-by-side manner, and a stiffener ring secured to the top surface of the package substrate. The stiffener ring encircles the first semiconductor die and the second semiconductor die. The stiffener ring comprises a reinforcement rib striding across the interposer.

公开(公告)号：US09184107B2

公开(公告)日：2015-11-10

申请号：US14585575

申请日：2014-12-30

Applicant: MediaTek Inc.

Inventor： Tai-Yu Chen ,  Chung-Fa Lee ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/373 ,  H01L23/36 ,  H01L23/433 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3736 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上，具有第一横截面尺寸; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在电路板上的密封剂层，覆盖半导体芯片并围绕间隔物; 形成在密封剂层和间隔物上的散热层; 以及形成在电路板的第二表面上的多个焊球，其中第一横截面尺寸和第二横截面尺寸之间的比率为约1：2-1：6。

公开(公告)号：US12087664B2

公开(公告)日：2024-09-10

申请号：US18129061

申请日：2023-03-30

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Sheng-Liang Kuo ,  Bo-Jiun Yang

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/16

CPC classification number: H01L23/473 ,  H01L23/16 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.

公开(公告)号：US20230307421A1

公开(公告)日：2023-09-28

申请号：US18203631

申请日：2023-05-30

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Tai-Yu Chen ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L24/17 ,  H10B80/00

Abstract: A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.

公开(公告)号：US20230307316A1

公开(公告)日：2023-09-28

申请号：US18116258

申请日：2023-03-01

Applicant: MEDIATEK INC.

Inventor： Chin-Lai Chen ,  Wei-Che Huang ,  Wen-Sung Hsu ,  Chun-Yin Lin ,  Li-Song Lin ,  Tai-Yu Chen

IPC: H01L23/427 ,  H01L23/16 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/427 ,  H01L23/16 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/32 ,  H01L2924/182 ,  H01L2224/16225 ,  H01L2224/32245

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface. A semiconductor device is mounted on the top surface of the substrate. The semiconductor device has an active front surface directly facing the substrate, and an opposite rear surface. A vapor chamber lid is in thermal contact with the rear surface of the semiconductor device. The vapor chamber lid includes an internal vacuum-sealed cavity that stores a working fluid, and wick structures for recirculating the working fluid within the internal vacuum-sealed cavity.