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    Reticles, And Methods Of Mitigating Asymmetric Lens Heating In Photolithography
    11.
    发明申请
    Reticles, And Methods Of Mitigating Asymmetric Lens Heating In Photolithography 审中-公开
    网格和减轻光刻中不对称透镜加热的方法

    公开(公告)号：US20150015860A1

    公开(公告)日：2015-01-15

    申请号：US14500625

    申请日：2014-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Scott L. Light ,  Dan Millward ,  Yuan He ,  Kaveri Jain ,  Lijing Gou ,  Zishu Zhang ,  Anton J. deVilliers ,  Michael D. Hyatt ,  Jianming Zhou

    IPC: G03F7/20

    CPC classification number: G03F7/70741 ,  G03F1/38 ,  G03F7/70433 ,  G03F7/70891

    Abstract: A method of mitigating asymmetric lens heating in photolithographically patterning a photo-imageable material using a reticle includes determining where first hot spot locations are expected to occur on a lens when using a reticle to pattern a photo-imageable material. The reticle is then fabricated to include non-printing features within a non-printing region of the reticle which generate additional hot spot locations on the lens when using the reticle to pattern the photo-imageable material. Other implementations are contemplated, including reticles which may be independent of method of use or fabrication.

    Abstract translation: 使用光掩模光刻地图案化可光成像材料的方法来减轻不对称透镜加热的方法包括当使用掩模版图案可光成像材料时，确定预期在透镜上将出现第一热点位置的位置。 然后制造掩模版以在掩模版的非印刷区域内包括非印刷特征，当使用掩模版对可光成像材料进行图案化时，其在透镜上产生额外的热点位置。 考虑了其他实施方式，包括可以独立于使用或制造方法的标线。

    SEMICONDUCTOR DEVICE STRUCTURES
    12.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES 有权
    半导体器件结构

    公开(公告)号：US20140353803A1

    公开(公告)日：2014-12-04

    申请号：US14457658

    申请日：2014-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Anton J. deVilliers

    IPC: H01L23/52

    CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed.

    Abstract translation: 公开了形成特征的方法。 一种方法包括在衬底结构上的酸性或碱性材料池上形成抗蚀剂，选择性地将抗蚀剂暴露于能量源以形成暴露的抗蚀剂部分和未曝光的抗蚀剂部分，以及将酸性或碱性材料的酸或碱扩散 从池中到抗蚀剂的近端部分。 另一种方法包括在衬底结构中形成多个凹陷。 多个凹部填充有包含酸或碱的池材料。 在池材料上形成抗蚀剂，并且衬底结构和酸或碱扩散到抗蚀剂的相邻部分。 抗蚀剂被图案化以在抗蚀剂中形成开口。 开口包括远离衬底结构的较宽部分和靠近衬底结构的较窄部分。 公开了包括这些特征的附加方法和半导体器件结构。

    Semiconductor device structures
    15.
    发明授权
    Semiconductor device structures 有权
    半导体器件结构

    公开(公告)号：US09142504B2

    公开(公告)日：2015-09-22

    申请号：US14457658

    申请日：2014-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Anton J. deVilliers

    IPC: H01L29/06 ,  H01L23/52 ,  H01L21/467 ,  H01L21/768 ,  H01L21/027

    CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed.

    Abstract translation: 公开了形成特征的方法。 一种方法包括在衬底结构上的酸性或碱性材料池上形成抗蚀剂，选择性地将抗蚀剂暴露于能量源以形成暴露的抗蚀剂部分和未曝光的抗蚀剂部分，以及将酸性或碱性材料的酸或碱扩散 从池中到抗蚀剂的近端部分。 另一种方法包括在衬底结构中形成多个凹陷。 多个凹部填充有包含酸或碱的池材料。 在池材料上形成抗蚀剂，并且衬底结构和酸或碱扩散到抗蚀剂的相邻部分。 抗蚀剂被图案化以在抗蚀剂中形成开口。 开口包括远离衬底结构的较宽部分和靠近衬底结构的较窄部分。 公开了包括这些特征的附加方法和半导体器件结构。

    METHODS OF FORMING FEATURES IN SEMICONDUCTOR DEVICE STRUCTURES
    17.
    发明申请
    METHODS OF FORMING FEATURES IN SEMICONDUCTOR DEVICE STRUCTURES 有权
    在半导体器件结构中形成特征的方法

    公开(公告)号：US20140145311A1

    公开(公告)日：2014-05-29

    申请号：US13687419

    申请日：2012-11-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Anton J. deVilliers

    IPC: H01L21/467 ,  H01L23/00 ,  H01L21/441

    CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed.

    Abstract translation: 公开了形成特征的方法。 一种方法包括在衬底结构上的酸性或碱性材料池上形成抗蚀剂，选择性地将抗蚀剂暴露于能量源以形成暴露的抗蚀剂部分和未曝光的抗蚀剂部分，以及将酸性或碱性材料的酸或碱扩散 从池中到抗蚀剂的近端部分。 另一种方法包括在衬底结构中形成多个凹陷。 多个凹部填充有包含酸或碱的池材料。 在池材料上形成抗蚀剂，并且衬底结构和酸或碱扩散到抗蚀剂的相邻部分。 抗蚀剂被图案化以在抗蚀剂中形成开口。 开口包括远离衬底结构的较宽部分和靠近衬底结构的较窄部分。 公开了包括这些特征的附加方法和半导体器件结构。

    INDUCTORS USING NAND LAYERS
    18.
    发明申请
    INDUCTORS USING NAND LAYERS 有权

    公开(公告)号：US20250085887A1

    公开(公告)日：2025-03-13

    申请号：US18777273

    申请日：2024-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Srivatsan Venkatesan ,  Kaveri Jain ,  Salil Shashikant Mujumdar ,  Rajat Vishnoi ,  Sushma Dogiparthi

    IPC: G06F3/06 ,  G11C16/04

    Abstract: An inductor is formed on an integrated circuit (IC) using one or more structures formed during or in coordination with 3D NAND structure fabrication with one or more modifications. The inductor has a staircase structure, the staircase structure having a plurality of tiers that form steps on one side of the staircase structure. Each tier comprises a conductive layer. The plurality of tiers includes at least a first tier and a second tier. The inductor has a first contact electrically coupling the first tier and the second tier. A first portion of a die is occupied by a memory sub-component comprising at least one three-dimensional (3D) NAND memory component and a second portion of the die is occupied by the inductor.

    PHOTOALIGNMENT OF SEMICONDUCTOR STRUCTURES USING AN OPAQUE HARDMASK
    19.
    发明申请
    PHOTOALIGNMENT OF SEMICONDUCTOR STRUCTURES USING AN OPAQUE HARDMASK 有权

    公开(公告)号：US20250006655A1

    公开(公告)日：2025-01-02

    申请号：US18750247

    申请日：2024-06-21

    Applicant: Micron Technology, Inc.

    Inventor： Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Lance David Williamson ,  Kaveri Jain ,  Adam Lewis Olson

    IPC: H01L23/544 ,  H01L21/311

    Abstract: Aligning pillars of a three-dimensional NAND memory assembly can include forming a first pillar and a corresponding first pillar alignment feature in at least a portion of a first substrate stack. The alignment method can include depositing a second substrate stack on the first substrate stack, covering the first pillar alignment feature and the first pillar, and depositing a first masking layer on at least a portion of the second substrate stack. Illumination light can be used to illuminate a portion of the first masking layer. A reflected portion of the illumination light can indicate a location of the first pillar alignment feature corresponding to the first pillar. Particular wavelengths of the illumination light can be blocked or filtered by the first masking layer.

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