公开(公告)号：US11923305B2

公开(公告)日：2024-03-05

申请号：US17076658

申请日：2020-10-21

Applicant: Micron Technology, Inc.

Inventor： Luca Fumagalli ,  Davide Colombo

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H10B12/00

CPC classification number: H01L23/53266 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/528 ,  H01L23/5329 ,  H10B12/00 ,  H10B12/30 ,  H10B12/482

Abstract: Some embodiments include an apparatus having a structure with a surface which comprises tungsten. The apparatus has titanium-nitride-containing protective material along and directly against the surface. The structure may be a digit line of a memory array. Some embodiments include a method in which an assembly is formed to have a tungsten-containing layer with an exposed tungsten-containing upper surface. Titanium-nitride-containing protective material is formed over and directly against the tungsten-containing upper surface. Additional material is formed over the protective material, and is spaced from the tungsten-containing upper surface by the protective material. The additional material may comprise silicon nitride and/or silicon dioxide.

公开(公告)号：US20240074153A1

公开(公告)日：2024-02-29

申请号：US17896039

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jaydip Guha ,  Marko Milojevic ,  Sau Ha Cheung ,  Luca Fumagalli

IPC: H01L27/108 ,  H01B1/02

CPC classification number: H01L27/10823 ,  H01B1/02 ,  H01L27/10876

Abstract: Methods, apparatuses, and systems related to conductive structures are described. An example conductive structure includes a first conductive material including a conductive metal nitride, where the first conductive material has a thickness of at least 0.5 nanometers, and a second conductive material including a conductive metal, where the second conductive material is disposed on a first surface of the first conductive material.

公开(公告)号：US20240038588A1

公开(公告)日：2024-02-01

申请号：US17815359

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Vinay Nair ,  Russell A. Benson ,  Christopher W. Petz ,  Si-Woo Lee ,  Silvia Borsari ,  Ping Chieh Chiang ,  Luca Fumagalli

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures. Conductive line structures are formed within the additional trenches and in contact with the conductive contact structures.

公开(公告)号：US20220302032A1

公开(公告)日：2022-09-22

申请号：US17806438

申请日：2022-06-10

Applicant: Micron Technology Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US10892224B2

公开(公告)日：2021-01-12

申请号：US15904683

申请日：2018-02-26

Applicant: Micron Technology, Inc.

Inventor： Luca Fumagalli ,  Davide Colombo

IPC: H01L23/52 ,  H01L23/532 ,  H01L23/528 ,  H01L27/108 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02

Abstract: Some embodiments include an apparatus having a structure with a surface which comprises tungsten. The apparatus has titanium-nitride-containing protective material along and directly against the surface. The structure may be a digit line of a memory array. Some embodiments include a method in which an assembly is formed to have a tungsten-containing layer with an exposed tungsten-containing upper surface. Titanium-nitride-containing protective material is formed over and directly against the tungsten-containing upper surface. Additional material is formed over the protective material, and is spaced from the tungsten-containing upper surface by the protective material. The additional material may comprise silicon nitride and/or silicon dioxide.

公开(公告)号：US20200321340A1

公开(公告)日：2020-10-08

申请号：US16906718

申请日：2020-06-19

Applicant: Micron Technology, Inc.

Inventor： Kentaro Ishii ,  Yongjun J. Hu ,  Amirhasan Nourbakhsh ,  Durai Vishak Nirmal Ramaswamy ,  Christopher W. Petz ,  Luca Fumagalli

IPC: H01L27/108

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

公开(公告)号：US09299929B2

公开(公告)日：2016-03-29

申请号：US14727106

申请日：2015-06-01

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  Luca Fumagalli

IPC: H01L21/8239 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625

Abstract: A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first chalcogenide compound, a second chalcogenide compound directly on the first nitrogenated carbon material, and a second nitrogenated carbon material directly on the second chalcogenide compound and directly on a second electrode. Other phase change memory cells are described. A method of forming a phase change memory cell and a phase change memory device are also described.

Abstract translation: 一种相变存储单元，包括在第一电极上的第一硫族化合物，直接位于第一硫属化物化合物上的第一含氮碳材料，直接位于第一氮化碳材料上的第二硫族化合物，以及直接位于第二硫族化物上的第二含氮碳材料 化合物并直接在第二电极上。 其他相变存储单元被描述。 还描述了形成相变存储单元和相变存储器件的方法。

公开(公告)号：US20240153541A1

公开(公告)日：2024-05-09

申请号：US18413671

申请日：2024-01-16

Applicant: Micron Technology, Inc.

Inventor： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC: G11C5/10 ,  G11C11/405 ,  H01L27/06 ,  H10B12/00

CPC classification number: G11C5/10 ,  G11C11/405 ,  H01L27/0688 ,  H01L28/60 ,  H10B12/30

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240136391A1

公开(公告)日：2024-04-25

申请号：US18047978

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Sanket S. Kelkar ,  Michael Mutch ,  Luca Fumagalli ,  Hisham Abdussamad Abbas ,  Brenda D. Kraus ,  Dojun Kim ,  Christopher W. Petz ,  Darwin Franseda Fan

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01G4/008 ,  H01G4/1218 ,  H01L27/10814 ,  H01L27/10852

Abstract: A microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. The capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. Related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.

公开(公告)号：US11915777B2

公开(公告)日：2024-02-27

申请号：US17669189

申请日：2022-02-10

Applicant: Micron Technology, Inc.

Inventor： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC: G11C11/24 ,  G11C5/10 ,  H01L49/02 ,  G11C11/405 ,  H01L27/06 ,  H10B12/00

CPC classification number: G11C5/10 ,  G11C11/405 ,  H01L27/0688 ,  H01L28/60 ,  H10B12/30

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.