公开(公告)号：US10890937B2

公开(公告)日：2021-01-12

申请号：US16193410

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Martin Saint-Laurent ,  Lam Ho ,  Carlos Andres Rodriguez Ancer ,  Bhavin Shah

IPC: G06F1/03 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/10 ,  H03K3/012 ,  H03K19/00 ,  H03K5/131 ,  H03K21/40

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

公开(公告)号：US10309838B2

公开(公告)日：2019-06-04

申请号：US15260194

申请日：2016-09-08

Applicant: QUALCOMM Incorporated

Inventor： Ali Akbar Merrikh ,  Martin Saint-Laurent ,  Mohammad Ghasemazar ,  Rajit Chandra ,  Mohamed Allam

IPC: G01K1/20 ,  G01K1/14 ,  G01K7/01 ,  G01K7/42 ,  G06F1/20 ,  G01K15/00

Abstract: A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.

公开(公告)号：US20160162432A1

公开(公告)日：2016-06-09

申请号：US15045282

申请日：2016-02-17

Applicant: QUALCOMM Incorporated

Inventor： Baker S. Mohammad ,  Paul D. Bassett ,  Martin Saint-Laurent

IPC: G06F13/40 ,  H03K5/15 ,  G06F13/42 ,  H03K3/356

CPC classification number: G06F13/4077 ,  G06F13/4072 ,  G06F13/4291 ,  H03K3/356069 ,  H03K3/356113 ,  H03K5/15 ,  Y02D10/14 ,  Y02D10/151

Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.

Abstract translation: 一种装置包括耦合到第一总线的第一驱动电路，其中第一驱动电路包括第一延迟元件。 第一延迟元件被配置为接收第一输入信号并产生第一输出信号。 当第一输入信号从逻辑高电平转换到逻辑低电平时，第一输出信号在第一延迟周期之后转变逻辑电平。 当第一输入信号从逻辑低电平转换到逻辑高电平时，第一输出信号在第二延迟周期之后转变逻辑电平。 第一延迟元件包括读出放大器。 第一驱动器电路被配置为通过第一总线发送第一输出信号。 该装置还包括被配置为在第二总线上传输第二输出信号的第二驱动器电路。

公开(公告)号：US09093995B2

公开(公告)日：2015-07-28

申请号：US13905052

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Kashyap Ramachandra Bellur ,  HariKrishna Chintarlapalli Reddy ,  Martin Saint-Laurent ,  Pratyush Kamal ,  Prayag Bhanubhai Patel ,  Esin Terzioglu

IPC: H03K3/012 ,  H03K3/037 ,  G06F17/50 ,  H03K3/356

CPC classification number: H03K3/037 ,  G06F17/5068 ,  G06F17/5081 ,  H03K3/012 ,  H03K3/356

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract translation: 电路包括脉冲锁存电路。 脉冲锁存电路包括第一多个晶体管。 第一多个晶体管中的一个或多个是扩散长度（LOD）保护的。

公开(公告)号：US20140354338A1

公开(公告)日：2014-12-04

申请号：US13905052

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Kashyap Ramachandra Bellur ,  HariKrishna Chintarlapalli Reddy ,  Martin Saint-Laurent ,  Pratyush Kamal ,  Prayag Bhanubhai Patel ,  Esin Terzioglu

IPC: H03K3/037 ,  G06F17/50

CPC classification number: H03K3/037 ,  G06F17/5068 ,  G06F17/5081 ,  H03K3/012 ,  H03K3/356

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract translation: 电路包括脉冲锁存电路。 脉冲锁存电路包括第一多个晶体管。 第一多个晶体管中的一个或多个是扩散长度（LOD）保护的。

公开(公告)号：US20140306735A1

公开(公告)日：2014-10-16

申请号：US13862015

申请日：2013-04-12

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。

公开(公告)号：US20140237275A1

公开(公告)日：2014-08-21

申请号：US13771075

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： Joseph Victor Zanotelli ,  Martin Saint-Laurent

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  Y02D10/152

Abstract: A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.

Abstract translation: 提供具有多Vt关键路径的处理器，其包括低Vt设备和高Vt设备。 如果处理器在高性能模式下运行，则会控制多Vt关键路径，以便使用低Vt设备。 相反，如果处理器在低功耗模式下工作，则控制多Vt关键路径以便使用高Vt器件。 以这种方式，避免了单个处理器核心可以在高性能模式和低功率模式下工作的多处理核心的复杂性。