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    FIN FIELD-EFFECT TRANSISTOR STATIC RANDOM ACCESS MEMORY DEVICES WITH P-CHANNEL METAL-OXIDE-SEMICONDUCTOR PASS GATE TRANSISTORS
    11.
    发明申请
    FIN FIELD-EFFECT TRANSISTOR STATIC RANDOM ACCESS MEMORY DEVICES WITH P-CHANNEL METAL-OXIDE-SEMICONDUCTOR PASS GATE TRANSISTORS 审中-公开
    具有P沟道金属氧化物半导体通路栅极晶体管的FIN场效应晶体管静态随机存取存储器件

    公开(公告)号：US20160043092A1

    公开(公告)日：2016-02-11

    申请号：US14454805

    申请日：2014-08-08

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

    IPC: H01L27/11

    CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

    Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

    Abstract translation: 互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元。 根据本公开的一个方面的CMOS SRAM单元包括位线和字线。 这种CMOS SRAM存储单元还包括具有至少第一p沟道器件的CMOS存储器单元，该第一p沟道器件包括与CMOS存储器单元的衬底材料不同的第一沟道材料，第一沟道材料具有大于 衬底材料的固有沟道迁移率，第一p沟道器件将CMOS存储器单元耦合到位线和字线。

    STRESS IN N-CHANNEL FIELD EFFECT TRANSISTORS
    12.
    发明申请
    STRESS IN N-CHANNEL FIELD EFFECT TRANSISTORS 审中-公开
    N沟道场效应晶体管中的应力

    公开(公告)号：US20160035891A1

    公开(公告)日：2016-02-04

    申请号：US14448548

    申请日：2014-07-31

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Junhao XU ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7843 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

    Abstract: A fin field-effect transistor (FinFET) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material. The stressor material is confined by the capping material to a region proximate the gate stack. The stressor material provides stress on the semiconductor fin proximate the gate stack.

    Abstract translation: 鳍状场效应晶体管（FinFET）包括在半导体鳍片的表面上的栅极堆叠。 半导体鳍片可以包括封盖材料和应力源材料。 应力源材料被封盖材料限制在靠近栅极叠层的区域。 应力源材料在靠近栅极堆叠的半导体鳍片上提供应力。

    SEVEN-TRANSISTOR STATIC RANDOM-ACCESS MEMORY BITCELL WITH REDUCED READ DISTURBANCE
    17.
    发明申请
    SEVEN-TRANSISTOR STATIC RANDOM-ACCESS MEMORY BITCELL WITH REDUCED READ DISTURBANCE 审中-公开
    具有减少读取干扰的七电极静态随机存取存储器

    公开(公告)号：US20160093365A1

    公开(公告)日：2016-03-31

    申请号：US14499149

    申请日：2014-09-27

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul SONG ,  Seong-Ook JUNG ,  Young Hwi YANG ,  Zhongze WANG ,  Choh Fei YEAP

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

    Abstract translation: 系统和方法涉及七晶体管静态随机存取存储器（7T SRAM）位单元，其包括具有第一上拉晶体管，第一下拉晶体管和第一存储节点的第一反相器，以及具有 第二上拉晶体管，第二下拉晶体管和第二存储节点。 第二存储节点耦合到第一上拉晶体管和第一下拉晶体管的栅极。 传输门被配置为在写入操作，待机模式和保持模式期间将第一存储节点选择性地耦合到第二上拉晶体管和第二下拉晶体管的栅极，并且选择性地将第一存储节点与 在读取操作期间第一上拉晶体管的栅极和第一下拉晶体管。 可以通过耦合到第一存储节点的存取晶体管来读取或写入7T SRAM位单元。

    HIGH DENSITY STATIC RANDOM ACCESS MEMORY ARRAY HAVING ADVANCED METAL PATTERNING
    18.
    发明申请
    HIGH DENSITY STATIC RANDOM ACCESS MEMORY ARRAY HAVING ADVANCED METAL PATTERNING 有权
    高密度静态随机访问存储阵列具有高级金属图案

    公开(公告)号：US20150333131A1

    公开(公告)日：2015-11-19

    申请号：US14281710

    申请日：2014-05-19

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

    IPC: H01L29/40 ,  H01L29/161 ,  H01L27/11

    CPC classification number: H01L29/401 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/161

    Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.

    Abstract translation: 提供了针对具有高级金属图案化的高密度静态随机存取存储器（SRAM）阵列的方法和装置。 在一个示例中，提供了一种用于制造SRAM的方法。 该方法包括使用自对准双图案化（SADP）技术形成在第一层中沿第一方向定向的多个基本平行的第一金属线。 该方法还包括在基本上垂直于第一方向的第二方向上使用切割掩模蚀刻基本平行的第一金属线，以将基本上平行的第一金属线分离成多个岛，该岛具有在第 第一方向和第二相对侧对准第二方向。 该方法还包括在第二层中形成沿第一方向定向的多个第二金属线。

    REDUCED HEIGHT M1 METAL LINES FOR LOCAL ON-CHIP ROUTING
    19.
    发明申请
    REDUCED HEIGHT M1 METAL LINES FOR LOCAL ON-CHIP ROUTING 有权
    降低高度M1金属线用于本地片上路由

    公开(公告)号：US20150262930A1

    公开(公告)日：2015-09-17

    申请号：US14206360

    申请日：2014-03-12

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri MOJUMDER ,  Mustafa BADAROGLU

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

    Abstract translation: 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

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