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    DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
    11.
    发明申请
    DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 失效
    用于增加铜互连结构中电磁寿命的电介质障碍层

    公开(公告)号：US20070190784A1

    公开(公告)日：2007-08-16

    申请号：US11736402

    申请日：2007-04-17

    申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

    发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

    摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

    摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改进的铜的粘合性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

    Interconnection capacitance reduction
    13.
    发明申请
    Interconnection capacitance reduction 审中-公开
    互连电容降低

    公开(公告)号：US20060035457A1

    公开(公告)日：2006-02-16

    申请号：US10915166

    申请日：2004-08-10

    申请人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

    发明人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837

    摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.

    摘要翻译： 对集成电路的制造方法的改进。 移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。 导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

    Integrated circuit process monitoring and metrology system
    14.
    发明申请
    Integrated circuit process monitoring and metrology system 有权

    公开(公告)号：US20050181615A1

    公开(公告)日：2005-08-18

    申请号：US11072127

    申请日：2005-03-04

    申请人： Peter Burke ,  Eric Kirchner ,  James Elmer

    发明人： Peter Burke ,  Eric Kirchner ,  James Elmer

    IPC分类号： H01L21/302 ,  H01L21/3105 ,  H01L21/66 ,  H01L21/76 ,  H01L23/544

    CPC分类号： H01L22/34 ,  H01L21/31053

    摘要： A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.

    Polishing pads for chemical mechanical planarization
    16.
    发明申请
    Polishing pads for chemical mechanical planarization 审中-公开

    公开(公告)号：US20050020082A1

    公开(公告)日：2005-01-27

    申请号：US10922715

    申请日：2004-08-20

    申请人： Arun Vishwanathan ,  David James ,  Lee Cook ,  Peter Burke ,  David Shidner

    发明人： Arun Vishwanathan ,  David James ,  Lee Cook ,  Peter Burke ,  David Shidner

    IPC分类号： B24B37/04 ,  B24D3/28 ,  B24D13/14 ,  B24B49/00 ,  B24B51/00 ,  H01L21/302 ,  H01L21/461

    CPC分类号： B24B37/26 ,  B24B37/042 ,  B24D3/28

    摘要： An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning. The benefits of such a polishing pad are low dishing of metal features, low oxide erosion, reduced pad conditioning, longer pad life, high metal removal rates, good planarization, and lower defectivity (scratches and Light Point Defects).