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    Dynamic memory rank configuration
    11.
    发明授权
    Dynamic memory rank configuration 有权

    公开(公告)号：US11244727B2

    公开(公告)日：2022-02-08

    申请号：US14940084

    申请日：2015-11-12

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent S. Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/06 ,  G11C13/00 ,  G11C16/26 ,  G11C7/04 ,  H01L21/324

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES
    12.
    发明申请
    FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES 有权

    公开(公告)号：US20210174875A1

    公开(公告)日：2021-06-10

    申请号：US16953182

    申请日：2020-11-19

    Applicant: Rambus Inc.

    Inventor： Brent S. Haukness ,  Ian Shaeffer ,  Gary Bela Bronner

    IPC: G11C16/10 ,  G06F3/06

    Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

    Reduced current memory device
    13.
    发明授权
    Reduced current memory device 有权

    公开(公告)号：US10224100B2

    公开(公告)日：2019-03-05

    申请号：US15100167

    申请日：2014-12-03

    Applicant: RAMBUS INC.

    Inventor： Deepak Chandra Sekar ,  Brent S. Haukness ,  Bruce L. Bateman

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00 ,  H01L27/24

    Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.

    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE
    14.
    发明申请
    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 审中-公开

    公开(公告)号：US20180107542A1

    公开(公告)日：2018-04-19

    申请号：US15794164

    申请日：2017-10-26

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1048

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    REDUCED REFRESH POWER
    15.
    发明申请
    REDUCED REFRESH POWER 有权
    降低刷新功率

    公开(公告)号：US20160027498A1

    公开(公告)日：2016-01-28

    申请号：US14801558

    申请日：2015-07-16

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Scott C. Best ,  Gary B. Bronner

    IPC: G11C11/406

    CPC classification number: G11C11/40611 ,  G11C2211/4061

    Abstract: N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.

    Abstract translation: 每个M个刷新命令中的N个被存储器模块上的缓冲器芯片忽略（滤除掉）。 N和M是可编程的。 缓冲器从命令地址信道接收刷新命令（例如，自动刷新命令），但不向模块上的DRAM发出这些命令的一部分。 这减少了刷新操作所消耗的功耗。 缓冲区可以用针对特定行的激活（ACT）和预充电（PRE）命令替换一些自动刷新（REF）命令。 这些行可能具有比模块（或组件）上的大多数其他行更频繁刷新的已知“弱”单元格。 通过忽略一些自动刷新命令，并将一些其他命令指向具有“弱”单元格的特定行，可以减少刷新操作消耗的功率。

    Patterned memory page activation
    17.
    发明授权
    Patterned memory page activation 有权
    图案化内存页激活

    公开(公告)号：US08873329B1

    公开(公告)日：2014-10-28

    申请号：US13741308

    申请日：2013-01-14

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  Brent S. Haukness

    IPC: G11C8/00 ,  G11C8/08

    CPC classification number: G11C8/08 ,  G11C5/04 ,  G11C8/10 ,  G11C8/14

    Abstract: Row activation operations within a memory component are carried out with respect to patterns of storage cells that constitute a fraction of a row and that have been predicted or predetermined to yield a succession of page hits, thus reducing activation power consumption without significantly increasing memory latency. The patterns of activated storage cells may be predicted or predetermined statically, for example, in response to user input or configuration settings that specify activation patterns to be applied in response to memory request traffic meeting various criteria, or dynamically through run-time evaluation of sequences of memory access requests.

    Abstract translation: 存储器组件内的行激活操作相对于构成行的一小部分并且已被预测或预定以产生一连串页面命中的存储单元的模式来执行，从而在不显着增加存储器等待时间的情况下降低激活功率消耗。 激活的存储单元的模式可以静态地预测或预定，例如，响应于用户输入或配置设置，其指定响应于满足各种标准的存储器请求流量而应用的激活模式，或动态地通过序列的运行时评估 的内存访问请求。

    Memory component with error-detect-correct code interface
    18.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US12130703B2

    公开(公告)日：2024-10-29

    申请号：US18230403

    申请日：2023-08-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: H03M13/27 ,  G06F11/10 ,  H03M13/25 ,  H04L1/00 ,  H04L27/34

    CPC classification number: G06F11/1076 ,  G06F11/1048

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    DRAM INTERFACE MODE WITH INTERRUPTIBLE INTERNAL TRANSFER OPERATION
    19.
    发明公开
    DRAM INTERFACE MODE WITH INTERRUPTIBLE INTERNAL TRANSFER OPERATION 审中-公开

    公开(公告)号：US20240152470A1

    公开(公告)日：2024-05-09

    申请号：US18388994

    申请日：2023-11-13

    Applicant: Rambus Inc.

    Inventor： Liji Gopalakrishnan ,  Frederick A. Ware ,  Brent S. Haukness

    IPC: G06F13/16 ,  G06F3/06

    CPC classification number: G06F13/1668 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0673

    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

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