公开(公告)号：US09258006B2

公开(公告)日：2016-02-09

申请号：US14711733

申请日：2015-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi Oshima ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/00 ,  H03M1/44 ,  H03M1/38 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/14 ,  H03M1/38 ,  H03M1/44 ,  H03M1/46 ,  H03M1/56

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

公开(公告)号：US08823565B2

公开(公告)日：2014-09-02

申请号：US13940819

申请日：2013-07-12

Applicant: Renesas Electronics Corporation

Inventor： Keisuke Kimura ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

IPC: H03M1/20

CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

公开(公告)号：US20130214947A1

公开(公告)日：2013-08-22

申请号：US13768811

申请日：2013-02-15

Applicant: IMEC ,  RENESAS ELECTRONICS CORPORATION

Inventor： Takaya Yamamoto ,  Jan Craninckx

IPC: H03M1/38

CPC classification number: H03M1/38 ,  G11C27/024 ,  H03M1/0854 ,  H03M1/129 ,  H03M1/46

Abstract: A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.

Abstract translation: 一种包括用于提供与输入模拟电流信号相关的信号的采样和保持电路的装置，通过对输入的模拟电流信号进行采样并将其积分在电容性装置上，从而将电容装置充电到电荷值。 电容性装置被配置为动态地改变其有效电容值，以形成存在于电容装置上的电压信号，使得电荷值保持不变。 该装置还包括模数转换（ADC）和控制电路，其被布置为在采样和保持电路的输出处执行至少一个相关信号的ADC作为输出数字信号，该ADC和控制电路包括连续的 近似ADC用于考虑电容装置上的电压信号的值并将存在于电容装置中的电荷值转换为数字输出信号。

公开(公告)号：US10310049B2

公开(公告)日：2019-06-04

申请号：US15218006

申请日：2016-07-23

Applicant: Renesas Electronics Corporation

Inventor： Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura ,  Takashi Oshima

IPC: G01R31/3163 ,  H03M1/10 ,  G01R19/25 ,  G01R35/00 ,  H03M1/46

Abstract: The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

公开(公告)号：US09960778B2

公开(公告)日：2018-05-01

申请号：US15472866

申请日：2017-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06

CPC classification number: H03M1/0607 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0629 ,  H01L2924/0002 ,  H03M1/0604 ,  H03M1/1023 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/442 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468 ,  H01L2924/00

Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.

公开(公告)号：US09362931B2

公开(公告)日：2016-06-07

申请号：US14750242

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Takaya Yamamoto ,  Hideo Nakane ,  Keisuke Kimura ,  Yuichi Okuda ,  Takashi Oshima

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/06 ,  H03M1/46 ,  H03M1/10

CPC classification number: H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/124 ,  H03M1/145 ,  H03M1/38 ,  H03M1/462 ,  H03M1/468

Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

Abstract translation: 提供了一种使用低功率和小面积的半导体器件，可以实现高精度的校准。 根据实施例的半导体器件包括A / D转换单元和耦合到A / D转换单元的输入侧的保持信号产生电路，并且具有不少于A / D转换单元的两个周期的保持周期， D转换单元。 保持信号生成电路包括：SC积分器，包括耦合到A / D转换单元的输入侧的输入缓冲器，以及耦合到输入缓冲器的输入和输出的反馈电容器; 以及将从A / D转换单元输出的多个比特的输出信号与第一和第二阈值进行比较的逻辑电路，并根据比较结果输出控制SC积分器的极性的控制信号。

公开(公告)号：US09007245B2

公开(公告)日：2015-04-14

申请号：US14445682

申请日：2014-07-29

Applicant: Renesas Electronics Corporation

Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

IPC: H03M1/20 ,  H03M3/00

CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

公开(公告)号：US08890733B2

公开(公告)日：2014-11-18

申请号：US13768811

申请日：2013-02-15

Applicant: IMEC ,  Renesas Electronics Corporation

Inventor： Takaya Yamamoto ,  Jan Craninckx

IPC: H03M1/12 ,  G11C27/02 ,  H03M1/38 ,  H03M1/08 ,  H03M1/46

CPC classification number: H03M1/38 ,  G11C27/024 ,  H03M1/0854 ,  H03M1/129 ,  H03M1/46

Abstract: A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.

Abstract translation: 一种包括用于提供与输入模拟电流信号相关的信号的采样和保持电路的装置，通过对输入的模拟电流信号进行采样并将其积分在电容性装置上，从而将电容装置充电到电荷值。 电容性装置被配置为动态地改变其有效电容值，以形成存在于电容装置上的电压信号，使得电荷值保持不变。 该装置还包括模数转换（ADC）和控制电路，其被布置为在采样和保持电路的输出处执行至少一个相关信号的ADC作为输出数字信号，该ADC和控制电路包括连续的 近似ADC用于考虑电容装置上的电压信号的值并将存在于电容装置中的电荷值转换为数字输出信号。

公开(公告)号：US08886141B2

公开(公告)日：2014-11-11

申请号：US13657765

申请日：2012-10-22

Applicant: RENESAS Electronics Corporation

Inventor： Hideo Nakane ,  Keisuke Kimura ,  Takaya Yamamoto ,  Tatsuji Matsuura ,  Ryuichi Ujiie

IPC: H04B17/02 ,  H03M1/10 ,  H04B1/10

CPC classification number: H03M1/1004 ,  H03M1/1009 ,  H04B1/1027

Abstract: Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing.

Abstract translation: 提供了能够在接收操作期间执行背景校准而不会不利地影响接收特性的半导体器件。 在接收操作期间，半导体器件检测在增益改变或接收信道改变时发生无效接收信号的定时，并在检测到的定时执行背景校准。 在这种情况下，由于接收信号无效，进行校准不会进一步降低接收的实质准确性。 此外，只要在随机定时执行背景校准，就不会产生当以固定间隔执行背景校准时将产生的不必要的信号分量。

公开(公告)号：US10020814B2

公开(公告)日：2018-07-10

申请号：US15594753

申请日：2017-05-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.