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公开(公告)号：US10825530B2
公开(公告)日：2020-11-03
申请号：US16226810
申请日：2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seong-Jin Song , Hyun-Wook Park , Bong-Soon Lim , Do-Bin Kim
Abstract: In a method of erasing data in a nonvolatile memory device including a memory block, it is determined whether a data erase characteristic for the memory block is degraded for each predetermined cycle. The memory block has a plurality of memory cells therein, the plurality of memory cells being stacked in a vertical direction relative to an underlying substrate. A data erase operation is performed by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.
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公开(公告)号：US10748617B2
公开(公告)日：2020-08-18
申请号：US16222038
申请日：2018-12-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kui-Han Ko , Jin-Young Kim , Il-Han Park , Bong-Soon Lim
IPC: G11C8/10 , G11C16/04 , G11C11/56 , G11C16/26 , G11C16/08 , G11C16/10 , H01L27/11582 , H01L27/11556
Abstract: A method of operating a nonvolatile memory device is provided where the nonvolatile memory device includes a plurality of cell strings, and each cell string includes a plurality of multi-level cells. a voltage of a selected word line is sequentially changed to sequentially have a plurality of read voltages for determining threshold voltage states of the plurality of multi-level cells. A voltage of an adjacent word line adjacent to the selected word line is sequentially changed in synchronization with voltage changing time points of the selected word line. A load of the selected word line is reduced and an operation speed of the nonvolatile memory device is increased by synchronizing the voltage change of the selected word line and the voltage change of the adjacent word line in the same direction.
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公开(公告)号：US10593408B2
公开(公告)日：2020-03-17
申请号：US16191656
申请日：2018-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： June-Hong Park , Ki-Whan Song , Bong-Soon Lim , Su-Chang Jeon , Jin-Young Kim , Chang-Yeon Yu , Dong-Kyo Shim , Seong-Jin Kim
Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
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公开(公告)号：US10446575B2
公开(公告)日：2019-10-15
申请号：US16014902
申请日：2018-06-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chan-Ho Kim , Bong-Soon Lim , Pan-Suk Kwak , Hong-Soo Jeon
IPC: H01L29/76 , H01L27/115 , H01L27/11582 , H01L27/11573 , G11C16/08 , G11C16/24 , H01L27/1157
Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.
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公开(公告)号：US10153050B2
公开(公告)日：2018-12-11
申请号：US15822320
申请日：2017-11-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae-Hyun Kim , Bong-Soon Lim , Yoon-Hee Choi , Sang-Won Shim
Abstract: A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11961564B2
公开(公告)日：2024-04-16
申请号：US17503952
申请日：2021-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang-Yeon Yu , Kui-Han Ko , Il-Han Park , June-Hong Park , Joo-Yong Park , Joon-Young Park , Bong-Soon Lim
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/0483
Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
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17.发明授权公开(公告)号：US11688478B2
公开(公告)日：2023-06-27
申请号：US17694229
申请日：2022-03-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seong-Jin Song , Hyun-Wook Park , Bong-Soon Lim , Do-Bin Kim
CPC classification number: G11C16/349 , G11C16/0483 , G11C16/14 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/05147 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.
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18.发明授权公开(公告)号：US11183249B2
公开(公告)日：2021-11-23
申请号：US16141147
申请日：2018-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang-Yeon Yu , Kui-Han Ko , Il-Han Park , June-Hong Park , Joo-Yong Park , Joon-Young Park , Bong-Soon Lim
IPC: G11C16/16 , G11C16/08 , G11C16/26 , G11C16/04 , G11C16/24 , G11C11/56 , G11C16/10 , H01L27/11556 , H01L27/1157 , H01L27/11582
Abstract: To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
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公开(公告)号：US20190139978A1
公开(公告)日：2019-05-09
申请号：US16014902
申请日：2018-06-21
Applicant: Samsung Electronics Co., Ltd
Inventor： CHAN-HO KIM , Bong-Soon Lim , Pan-Suk Kwak , Hong-Soo Jeon
IPC: H01L27/11582 , H01L27/11573 , H01L27/1157 , G11C16/24 , G11C16/08
Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.
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公开(公告)号：US20180268921A1
公开(公告)日：2018-09-20
申请号：US15824068
申请日：2017-11-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ho-Jun Lee , Bong-Soon Lim , Sang-Won Park
CPC classification number: G11C29/765 , G06F12/0246 , G06F2212/7201 , G06F2212/7204 , G11C29/88 , G11C29/883
Abstract: A nonvolatile memory device includes a memory cell array and a bad block remapping circuit. The memory cell array includes a first mat and a second mat that are paired with each other. The first mat includes a plurality of first memory blocks. The second mat includes a plurality of second memory blocks. A first selection memory block among the plurality of first memory blocks and a second selection memory block among the plurality of second memory blocks are accessed based on a first address. The bad block remapping circuit generates a first remapping address based on the first address when it is determined that the first selection memory block is defective. A first remapping memory block among the plurality of first memory blocks and the second selection memory block are accessed based on the first remapping address.
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