公开(公告)号：US09287116B2

公开(公告)日：2016-03-15

申请号：US14309128

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwansoo Suh ,  Insu Jeon ,  Young-jae Song ,  Qinke Wu ,  Seong-jun Jung

IPC: H01L29/15 ,  H01L21/02

CPC classification number: H01L21/02527 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0262 ,  H01L21/02664

Abstract: According to example embodiments, a method of forming a multilayer graphene structure includes forming a sacrificial layer on the growth substrate, growing a first graphene layer on the sacrificial layer using a chemical vapor deposition (CVD) method, and growing at least one more graphene layer on the growth substrate. The growing at least one more graphene layer includes removing at least a part of the sacrificial layer.

Abstract translation: 根据示例性实施例，形成多层石墨烯结构的方法包括在生长衬底上形成牺牲层，使用化学气相沉积（CVD）方法在牺牲层上生长第一石墨烯层，并且生长至少一个以上石墨烯层 在生长底物上。 生长至少一个以上的石墨烯层包括去除牺牲层的至少一部分。

公开(公告)号：US20240363989A1

公开(公告)日：2024-10-31

申请号：US18770206

申请日：2024-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeong Lee ,  Hyeokshin Kwon ,  Jaeho Shin ,  Taehwan Jang ,  Insu Jeon

IPC: H01P3/00 ,  G06N10/00 ,  H01P7/08

CPC classification number: H01P3/003 ,  G06N10/00 ,  H01P7/086

Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.

公开(公告)号：US11812672B2

公开(公告)日：2023-11-07

申请号：US17227661

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyeokshin Kwon ,  Jaehyeong Lee ,  Insu Jeon

IPC: H10N60/12 ,  G06N10/00 ,  H10N60/80

CPC classification number: H10N60/12 ,  G06N10/00 ,  H10N60/805

Abstract: Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.

公开(公告)号：US11245021B2

公开(公告)日：2022-02-08

申请号：US17028205

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Jinwook Jung ,  Hyeokshin Kwon ,  Wontaek Seo ,  Insu Jeon

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/16

Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

公开(公告)号：US10818765B2

公开(公告)日：2020-10-27

申请号：US16356378

申请日：2019-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Jinwook Jung ,  Hyeokshin Kwon ,  Wontaek Seo ,  Insu Jeon

IPC: H01L29/45 ,  H01L29/16 ,  H01L29/786

Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

公开(公告)号：US10126146B2

公开(公告)日：2018-11-13

申请号：US14697038

申请日：2015-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hwansoo Suh ,  Insu Jeon ,  Jhinhwan Lee

IPC: G01D5/12 ,  G01B7/00 ,  G01Q10/04 ,  G01Q20/04

Abstract: A piezoelectric actuator and a method of measuring a motion by using the piezoelectric actuator are provided. The piezoelectric actuator includes: a movable member that is disposed to face the fixed member; a piezoelectric element that is disposed between the fixed member and the movable member, and configured to operate in a shear mode based on input voltages applied to the piezoelectric element and move the movable member relative to the fixed member; and a position sensor that is disposed between the piezoelectric element and the movable member, and configured to measure a motion of the movable member.

公开(公告)号：US09899473B2

公开(公告)日：2018-02-20

申请号：US15261229

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek Oh ,  Hyeokshin Kwon ,  Hwansoo Suh ,  Insu Jeon

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/16 ,  H01L21/02 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02425 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02601 ,  H01L21/02603 ,  H01L21/02631 ,  H01L21/02639 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/861

Abstract: Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer. The insulating layer may have a crystal structure. The insulating layer may include an insulating two-dimensional (2D) material. The insulating 2D material may include a hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer. The nanostructure may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire.

公开(公告)号：US09368177B2

公开(公告)日：2016-06-14

申请号：US14282470

申请日：2014-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwansoo Suh ,  Insu Jeon ,  Min-woo Kim ,  Young-jae Song ,  Min Wang ,  Qinke Wu ,  Sung-joo Lee ,  Sung-kyu Jang ,  Seong-jun Jung

IPC: H01L29/66 ,  G11C11/16 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C2213/35 ,  H01L27/22 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12 ,  Y10T428/30

Abstract: Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic resistance structure. The method of manufacturing the magnetic resistance structure includes forming a hexagonal boron nitride layer, forming a graphene layer on the boron nitride layer, forming a first magnetic material layer between the boron nitride layer and the graphene layer according to an intercalation process; and forming a second magnetic material layer on the graphene layer.

Abstract translation: 提供磁阻结构，制造磁阻结构的方法以及包括磁阻结构的电子器件。 制造磁阻结构的方法包括：形成六方氮化硼层，在氮化硼层上形成石墨烯层，根据嵌入工艺在氮化硼层和石墨烯层之间形成第一磁性材料层; 以及在所述石墨烯层上形成第二磁性材料层。