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    Driving method of memory controller and nonvolatile memory device controlled by memory controller
    13.
    发明授权
    Driving method of memory controller and nonvolatile memory device controlled by memory controller 有权
    由存储器控制器控制的存储器控​​制器和非易失性存储器件的驱动方法

    公开(公告)号：US09594673B2

    公开(公告)日：2017-03-14

    申请号：US14523978

    申请日：2014-10-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungryun Kim ,  Seokjun Ham

    IPC: G06F12/02 ,  G06F11/10 ,  G11C29/52 ,  G11C29/44

    CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F2212/7211 ,  G11C29/52 ,  G11C2029/4402

    Abstract: A method is for driving a memory controller which is configured to control a nonvolatile memory device. The method includes counting a number of error bits of read data provided from the nonvolatile memory device, determining a running average value using the number of error bits; and performing a wear leveling on the nonvolatile memory device using the running average value as a wear leveling index.

    Abstract translation: 一种用于驱动被配置为控制非易失性存储器件的存储器控​​制器的方法。 该方法包括对从非易失性存储器件提供的读取数据的错误位数进行计数，使用错误位数确定运行平均值; 以及使用所述运行平均值作为磨损平衡指数，在所述非易失性存储装置上执行磨损均衡。

    Voltage trimming circuit
    15.
    发明授权
    Voltage trimming circuit 有权

    公开(公告)号：US11776644B2

    公开(公告)日：2023-10-03

    申请号：US17591987

    申请日：2022-02-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minho Choi ,  Jaeseong Lim ,  Kyungryun Kim ,  Daehyun Kim ,  Wonil Bae ,  Hohyun Shin ,  Sanghoon Jung ,  Hyongryol Hwang

    IPC: G11C17/18 ,  G11C29/08 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/08

    Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    17.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11094390B2

    公开(公告)日：2021-08-17

    申请号：US16795730

    申请日：2020-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

    IPC: G11C29/18 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

    Storage and programming method thereof
    18.
    发明授权
    Storage and programming method thereof 有权

    公开(公告)号：US09875793B2

    公开(公告)日：2018-01-23

    申请号：US15176964

    申请日：2016-06-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim ,  Sangyong Yoon

    IPC: G06F12/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G06F12/10

    CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F12/10 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30

    Abstract: A program method of a storage device which includes at least one nonvolatile memory device and a memory controller to control the at least one nonvolatile memory device, the program method comprising: performing a first normal program operation to store first user data in a memory block; detecting, at the memory controller, a first event; performing a dummy program operation to store dummy data in at least one page of the memory block in response to the detection of the first event; and performing a second normal program operation to store second user data in the memory block after the dummy program operation, dummy program operations being operations in which random data is programmed into the memory block, normal program operations being operations in which data other than random data is programmed in the memory block.

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