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    Page buffer circuit and memory device including the same
    11.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US11568903B2

    公开(公告)日：2023-01-31

    申请号：US17222024

    申请日：2021-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

    IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C16/34

    Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

    Memory device having an increased sensing margin
    12.
    发明授权
    Memory device having an increased sensing margin 有权

    公开(公告)号：US11011228B2

    公开(公告)日：2021-05-18

    申请号：US16741153

    申请日：2020-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongsung Cho ,  Taehui Na ,  Junho Shin ,  Makoto Hirano

    IPC: G11C13/00

    Abstract: A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.

    Memory device, operation method of memory device, and page buffer included in memory device
    14.
    发明授权
    Memory device, operation method of memory device, and page buffer included in memory device 有权

    公开(公告)号：US12198782B2

    公开(公告)日：2025-01-14

    申请号：US18449864

    申请日：2023-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Min Hwi Kim ,  Ji-Sang Lee

    IPC: G11C7/20 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

    Page buffer circuit and memory device including the same
    16.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US12057173B2

    公开(公告)日：2024-08-06

    申请号：US17836453

    申请日：2022-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho

    IPC: G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/26

    Abstract: A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.

    Memory device including row decoders
    17.
    发明授权
    Memory device including row decoders 有权

    公开(公告)号：US11437088B2

    公开(公告)日：2022-09-06

    申请号：US17239655

    申请日：2021-04-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngjae Kim ,  Jincheol Kim ,  Ahreum Kim ,  Homoon Shin ,  Dooho Cho ,  Yongsung Cho

    IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4093 ,  G11C5/06

    Abstract: A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.

    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    18.
    发明申请
    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220068322A1

    公开(公告)日：2022-03-03

    申请号：US17222024

    申请日：2021-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

    IPC: G11C7/06 ,  G11C7/10 ,  G11C16/34

    Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

    Nonvolatile memory device having adjustable program pulse width
    19.
    发明授权
    Nonvolatile memory device having adjustable program pulse width 有权
    具有可调程序脉冲宽度的非易失性存储器件

    公开(公告)号：US09064545B2

    公开(公告)日：2015-06-23

    申请号：US13721859

    申请日：2012-12-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongsung Cho ,  Kihwan Choi ,  Il Han Park ,  Kiwhan Song ,  Sangyong Yoon

    IPC: G11C16/04 ,  G11C7/04 ,  G11C16/10

    CPC classification number: G11C7/04 ,  G11C16/0483 ,  G11C16/10

    Abstract: A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line.

    Abstract translation: 非易失性存储器件的编程方法包括：确定非易失性存储器件的温度状态，根据温度条件确定编程脉冲周期，使用编程脉冲周期向选定字线提供编程电压，并提供通过电压 在将程序电压提供给所选择的字线的同时，将其作为未选择的字线。

    Memory device including vertical channel structure
    20.
    发明授权
    Memory device including vertical channel structure 有权

    公开(公告)号：US12300329B2

    公开(公告)日：2025-05-13

    申请号：US17881039

    申请日：2022-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Minjae Seo ,  Kyoman Kang ,  Byungsoo Kim

    IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

    Abstract: Provided is a memory device with a vertical channel structure. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.

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