公开(公告)号：US20170162687A1

公开(公告)日：2017-06-08

申请号：US15432961

申请日：2017-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Kazuya HANAOKA ,  Suguru HONDO ,  Shunpei YAMAZAKI

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

公开(公告)号：US20160329434A1

公开(公告)日：2016-11-10

申请号：US15144123

申请日：2016-05-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Daigo ITO ,  Takahisa ISHIYAMA ,  Katsuaki TOCHIBAYASHI ,  Kazuya HANAOKA

IPC: H01L29/786 ,  G11C13/00 ,  G06F1/06 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L21/67207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/1464 ,  H01L29/045 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The semiconductor device includes a first insulating layer; a first oxide insulating layer over the first insulating layer; an oxide semiconductor layer over the first oxide insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a second oxide insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer over the second oxide insulating layer; a gate electrode layer over the gate insulating layer; a second insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer; and a third insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, and the second insulating layer.

Abstract translation: 半导体器件包括第一绝缘层; 第一绝缘层上的第一氧化物绝缘层; 在所述第一氧化物绝缘层上的氧化物半导体层; 氧化物半导体层上的源电极层和漏电极层; 氧化物半导体层上的第二氧化物绝缘层，源电极层和漏电极层; 在所述第二氧化物绝缘层上的栅极绝缘层; 栅绝缘层上的栅电极层; 第一绝缘层上的第二绝缘层，源极电极层，漏极电极层，第二氧化物绝缘层，栅极绝缘层和栅极电极层; 以及第一绝缘层上的第三绝缘层，源极电极层，漏极电极层和第二绝缘层。

公开(公告)号：US20160093642A1

公开(公告)日：2016-03-31

申请号：US14961061

申请日：2015-12-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Yutaka OKAZAKI ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L27/12 ,  H01L27/115 ,  H01L29/417 ,  H01L29/10 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

公开(公告)号：US20150214041A1

公开(公告)日：2015-07-30

申请号：US14678134

申请日：2015-04-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuya HANAOKA ,  Shinya SASAGAWA

IPC: H01L21/02

CPC classification number: H01L21/02244 ,  H01L21/02107 ,  H01L21/02252 ,  H01L21/02323 ,  H01L21/02521 ,  H01L27/1156 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: In a processing method of a stacked-layer film in which a metal film is provided on an oxide insulating film, plasma containing an oxygen ion is generated by applying high-frequency power with power density greater than or equal to 0.59 W/cm2 and less than or equal to 1.18 W/cm2 to the stacked-layer film side under an atmosphere containing oxygen in which pressure is greater than or equal to 5 Pa and less than or equal to 15 Pa, the metal film is oxidized by the oxygen ion, and an oxide insulating film containing excess oxygen is formed by supplying oxygen to the oxide insulating film.

Abstract translation: 在氧化物绝缘膜上设置有金属膜的叠层膜的处理方法中，通过施加功率密度大于等于0.59W / cm 2的高频电力产生含有氧离子的等离子体 在含有大于或等于5Pa且小于或等于15Pa的氧的气氛下，叠层层一侧的厚度为1.18W / cm 2以下，金属膜被氧离子氧化， 并且通过向氧化物绝缘膜供给氧而形成含有过量氧的氧化物绝缘膜。

公开(公告)号：US20160056272A1

公开(公告)日：2016-02-25

申请号：US14885545

申请日：2015-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Hideomi SUZAWA ,  Kazuya HANAOKA

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: To provide a semiconductor device having a structure capable of suppressing deterioration of its electrical characteristics which becomes apparent with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode over the gate insulating film. A first interface between the gate electrode and the gate insulating film has a region closer to the insulating surface than a second interface between the first oxide semiconductor film and the second oxide semiconductor film.

Abstract translation: 提供具有能够抑制其电特性劣化的结构的半导体器件，其在小型化时变得明显。 半导体器件包括绝缘表面上的第一氧化物半导体膜; 第一氧化物半导体膜上的第二氧化物半导体膜; 与第二氧化物半导体膜接触的源电极和漏电极; 第二氧化物半导体膜上的第三氧化物半导体膜，源电极和漏电极; 第三氧化物半导体膜上的栅极绝缘膜; 以及栅极绝缘膜上的栅电极。 栅电极和栅绝缘膜之间的第一界面具有比第一氧化物半导体膜和第二氧化物半导体膜之间的第二界面更接近绝缘表面的区域。

公开(公告)号：US20140319516A1

公开(公告)日：2014-10-30

申请号：US14258553

申请日：2014-04-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Kazuya HANAOKA

IPC: H01L29/786

CPC classification number: H01L29/78618 ,  H01L29/41733 ,  H01L29/7869

Abstract: To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device formed using an oxide semiconductor and having favorable electrical characteristics. A semiconductor device includes an island-shaped semiconductor layer over an insulating surface; a pair of electrodes in contact with a side surface of the semiconductor layer and overlapping with a part of a top surface of the semiconductor layer; an oxide layer located between the semiconductor layer and the electrode and in contact with a part of the top surface of the semiconductor layer and a part of a bottom surface of the electrode; a gate electrode overlapping with the semiconductor layer; and a gate insulating layer between the semiconductor layer and the gate electrode. In addition, the semiconductor layer includes an oxide semiconductor, and the pair of electrodes includes Al, Cr, Cu, Ta, Ti, Mo, or W.

Abstract translation: 提供适合小型化的半导体器件。 提供高度可靠的半导体器件。 提供使用氧化物半导体形成并具有良好电气特性的半导体器件。 半导体器件包括绝缘表面上的岛状半导体层; 与半导体层的侧表面接触并与半导体层的顶表面的一部分重叠的一对电极; 位于半导体层和电极之间并与半导体层的顶表面的一部分和电极的底表面的一部分接触的氧化物层; 与半导体层重叠的栅电极; 以及在半导体层和栅电极之间的栅极绝缘层。 此外，半导体层包括氧化物半导体，该对电极包括Al，Cr，Cu，Ta，Ti，Mo或W.

公开(公告)号：US20140252351A1

公开(公告)日：2014-09-11

申请号：US14284733

申请日：2014-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Yutaka OKAZAKI ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Abstract translation: 在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜，通过使用经受电子束曝光的抗蚀剂选择性蚀刻第一导电膜形成栅电极，在栅绝缘膜上形成第一绝缘膜 和栅电极，在栅电极未被露出的同时去除第一绝缘膜的一部分，在第一绝缘膜，抗反射膜，第一绝缘膜和栅极绝缘膜上形成防反射膜 使用经受电子束曝光的抗蚀剂选择性蚀刻，以及与氧化物半导体膜的一端接触的源极和与氧化物半导体膜的另一端接触的第一绝缘膜和漏电极的一端，以及 形成第一绝缘膜的另一端。

公开(公告)号：US20130092925A1

公开(公告)日：2013-04-18

申请号：US13632635

申请日：2012-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

公开(公告)号：US20240355930A1

公开(公告)日：2024-10-24

申请号：US18626777

申请日：2024-04-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuya HANAOKA ,  Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI ,  Shunpei YAMAZAKI ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/785 ,  H01L29/7854

Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.

公开(公告)号：US20180248010A1

公开(公告)日：2018-08-30

申请号：US15903097

申请日：2018-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/423 ,  H01L27/146

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.