公开(公告)号：US09899424B2

公开(公告)日：2018-02-20

申请号：US15606465

申请日：2017-05-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Tatsuya Onuki

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.

公开(公告)号：US09870816B2

公开(公告)日：2018-01-16

申请号：US14527310

申请日：2014-10-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato

IPC: G11C11/404 ,  G11C11/417 ,  G11C11/412 ,  H01L27/108 ,  G11C11/405

CPC classification number: G11C11/417 ,  G11C11/404 ,  G11C11/405 ,  G11C11/412 ,  H01L27/108

Abstract: A semiconductor device includes SRAM that stores data in an inverter loop including a CMOS inverter, transistors electrically connected to an input terminal or an output terminal of the CMOS inverter, and capacitors electrically connected to the corresponding transistors. The semiconductor device is configured to hold potentials corresponding to data at nodes between the transistors and the corresponding capacitors in a period during which supply of power to the CMOS inverter stops. In the period during which power supply stops, the potential of a wiring applying a low power supply potential is made equal to a high power supply potential to make the potentials of the input and output terminals of the CMOS inverter equal to the high power supply potential. The potentials corresponding to the data held at the nodes are applied to the input and output terminals of the CMOS inverter to restart power supply.

公开(公告)号：US09865325B2

公开(公告)日：2018-01-09

申请号：US15296309

申请日：2016-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C11/34 ,  G11C11/4091 ,  G11C11/4097 ,  H01L29/786 ,  H01L27/108 ,  G11C7/10 ,  G11C11/4094 ,  G11C29/04

CPC classification number: G11C11/4091 ,  G11C7/1069 ,  G11C11/4094 ,  G11C11/4097 ,  G11C29/04 ,  H01L27/10805 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.

公开(公告)号：US09741400B2

公开(公告)日：2017-08-22

申请号：US15341707

申请日：2016-11-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Tomokazu Yokoi ,  Naoaki Tsutsui ,  Kazuaki Ohshima ,  Tatsuya Onuki

IPC: G11C7/10 ,  G11C7/06 ,  H01L27/11582 ,  H01L27/11568 ,  G11C5/06 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.

公开(公告)号：US09666725B2

公开(公告)日：2017-05-30

申请号：US15393356

申请日：2016-12-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Tatsuya Onuki

IPC: G11C11/404 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G11C11/404 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124

Abstract: A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.

公开(公告)号：US09666606B2

公开(公告)日：2017-05-30

申请号：US15232143

申请日：2016-08-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Tatsuya Onuki

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.

公开(公告)号：US09646677B2

公开(公告)日：2017-05-09

申请号：US15183971

申请日：2016-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C11/4096 ,  G11C7/00 ,  G11C5/06 ,  G11C5/14 ,  G11C11/56 ,  G11C29/02 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  G11C5/10 ,  G11C29/12

CPC classification number: G11C11/4096 ,  G11C5/06 ,  G11C5/10 ,  G11C5/147 ,  G11C7/00 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/5628 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1204

Abstract: Provided is a semiconductor device including first to fifth circuits. The first circuit includes first and second transistors. The second circuit is capable of supplying one of first and second wirings with a gradually changing potential. The third circuit is capable of supplying a predetermined potential to the other of the first and second wirings and is capable of reading data stored in the first circuit. The fourth circuit is capable of comparing first data to be written to the first circuit with second data read by the third circuit. When a comparison result obtained by the fourth circuit concludes that the first data is consistent with the second data, the fifth circuit disconnects the second circuit from the first circuit, and a potential of the one of the first and second wirings is supplied to a gate of the second transistor.

公开(公告)号：US09627010B2

公开(公告)日：2017-04-18

申请号：US14659914

申请日：2015-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Kiyoshi Kato ,  Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C5/14 ,  G11C11/409 ,  G11C11/4074 ,  G11C11/419

CPC classification number: G11C5/147 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/419 ,  G11C14/0054

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

公开(公告)号：US09478276B2

公开(公告)日：2016-10-25

申请号：US14679111

申请日：2015-04-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C11/24 ,  G11C11/4091 ,  G11C11/4097 ,  H01L29/786 ,  H01L27/108 ,  G11C7/10 ,  G11C11/4094 ,  G11C29/04

CPC classification number: G11C11/4091 ,  G11C7/1069 ,  G11C11/4094 ,  G11C11/4097 ,  G11C29/04 ,  H01L27/10805 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.

Abstract translation: 提供了具有减小的布局面积的存储器件。 存储器件包括电连接到第一和第二布线并位于第一层中的读出放大器，以及位于第一层上的第二层中的第一和第二电路。 第一电路包括根据第三布线的电位而导通和截止的第一开关，以及经由第一开关电连接到第一布线的第一电容器。 第二电路包括根据第四布线的电位而导通和截止的第二开关，以及通过第二开关电连接到第二布线的第二电容器。 第一布线与第三布线相交，并且不与第二层中的第四布线相交。 第二布线与第四布线相交，并且不与第二层中的第三布线相交。

公开(公告)号：US09196626B2

公开(公告)日：2015-11-24

申请号：US14272853

申请日：2014-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/115 ,  H01L27/108 ,  G11C11/00 ,  H01L27/105 ,  H01L27/11

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.