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    Nonvolatile memory cells with a vertical selection gate of variable depth
    11.
    发明授权
    Nonvolatile memory cells with a vertical selection gate of variable depth 有权
    具有可变深度的垂直选择栅极的非易失性存储单元

    公开(公告)号：US08901634B2

    公开(公告)日：2014-12-02

    申请号：US13786213

    申请日：2013-03-05

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Yoann Goasduff ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L29/788 ,  G11C16/04 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/7889 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L29/66825

    Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.

    Abstract translation: 本公开涉及一种集成电路，其包括形成在半导体衬底中的至少两个存储单元和与存储单元的选择晶体管共同的掩埋栅极。 掩埋栅极具有在选择晶体管的垂直沟道区域的前面延伸的第一深度的第一部分，以及大于深入埋入源极线的第一深度的至少第二深度的第二部分。 掩埋栅极的下侧由形成选择晶体管的源极区域的掺杂区域界定，并且在埋入栅极的第二部分穿入埋入源极线的水平面到达掩埋源极线，由此源极区域 耦合到埋地源线。

    Co-integrated vertically structured capacitive element and fabrication process
    13.
    发明授权
    Co-integrated vertically structured capacitive element and fabrication process 有权

    公开(公告)号：US11626365B2

    公开(公告)日：2023-04-11

    申请号：US17226324

    申请日：2021-04-09

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel

    IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

    Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

    Structure and Method of Forming a Semiconductor Device
    15.
    发明申请
    Structure and Method of Forming a Semiconductor Device 有权

    公开(公告)号：US20210066510A1

    公开(公告)日：2021-03-04

    申请号：US16560810

    申请日：2019-09-04

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L29/861 ,  H01L27/07 ,  H01L29/66 ,  H01L29/788

    Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.

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