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公开(公告)号：US12096640B2
公开(公告)日：2024-09-17
申请号：US18193965
申请日：2023-03-31
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe Boivin
CPC classification number: H10B63/24 , H10N70/021 , H10N70/063 , H10N70/231
Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.
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公开(公告)号：US10714501B2
公开(公告)日：2020-07-14
申请号：US16057466
申请日：2018-08-07
Inventor： Jean-Jacques Fagot , Philippe Boivin , Franck Arnaud
IPC: H01L27/12 , H01L21/762 , H01L21/84 , H01L29/808 , H01L27/06
Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
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公开(公告)号：US10304775B2
公开(公告)日：2019-05-28
申请号：US15700960
申请日：2017-09-11
Inventor： Philippe Boivin , Delia Ristoiu
IPC: H01L23/535 , H01L23/48 , H01L21/768 , H01L23/485 , H01L27/12 , H01L23/532
Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.
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公开(公告)号：US20180012935A1
公开(公告)日：2018-01-11
申请号：US15694463
申请日：2017-09-01
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US20170271325A1
公开(公告)日：2017-09-21
申请号：US15454788
申请日：2017-03-09
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Olivier Weber , Emmanuel Richard , Philippe Boivin
IPC: H01L27/06 , H01L27/24 , H01L29/732 , H01L21/84 , H01L21/8249 , H01L45/00
CPC classification number: H01L27/0623 , H01L21/8249 , H01L21/84 , H01L27/1207 , H01L27/2445 , H01L29/0813 , H01L29/41708 , H01L29/66303 , H01L29/732 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/126 , H01L45/16
Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
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Patent Agency Ranking
公开(公告)号：US08830761B2
公开(公告)日：2014-09-09
申请号：US13786202
申请日：2013-03-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa , Olivier Pizzuto , Stephan Niel , Philippe Boivin , Pascal Fornara , Laurent Lopez , Arnaud Regnier
IPC: G11C16/26 , G11C16/24 , G11C16/34 , G11C16/14 , G11C16/08 , H01L29/423 , H01L29/788 , H01L27/115 , G11C16/04 , G11C11/56 , G11C8/12
CPC classification number: G11C16/26 , G11C8/12 , G11C11/5642 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/24 , H01L27/11524 , H01L27/11556 , H01L29/42328 , H01L29/7881
Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.
Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。
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公开(公告)号：US12262649B2
公开(公告)日：2025-03-25
申请号：US17508754
申请日：2021-10-22
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe Boivin
Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
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公开(公告)号：US11818901B2
公开(公告)日：2023-11-14
申请号：US17489425
申请日：2021-09-29
Inventor： Philippe Boivin , Jean Jacques Fagot , Emmanuel Petitprez , Emeline Souchier , Olivier Weber
IPC: H01L21/8222 , H10B63/00 , H10N70/20 , H10N70/00
CPC classification number: H10B63/32 , H10N70/231 , H10N70/826
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
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公开(公告)号：US11653582B2
公开(公告)日：2023-05-16
申请号：US16184246
申请日：2018-11-08
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
CPC classification number: H10N70/8616 , G11C13/0004 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/882 , G11C2013/008
Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
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公开(公告)号：US11211428B2
公开(公告)日：2021-12-28
申请号：US16375557
申请日：2019-04-04
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe Boivin
IPC: H01L27/24 , H01L21/8222 , H01L27/082 , H01L29/10 , H01L45/00
Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.
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