公开(公告)号：US20180374859A1

公开(公告)日：2018-12-27

申请号：US16115711

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US10096605B2

公开(公告)日：2018-10-09

申请号：US15680960

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L29/06 ,  H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US09870950B2

公开(公告)日：2018-01-16

申请号：US15371646

申请日：2016-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Sun Hwang ,  Ja-Eung Koo ,  Jong-Hyung Park ,  Ho-Young Kim ,  Leian Bartolome ,  Bo-Un Yoon ,  Hyoung-Bin Moon

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28008 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L28/00 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

公开(公告)号：US09136135B2

公开(公告)日：2015-09-15

申请号：US13944087

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jik Baek ,  Ji-Hoon Cha ,  Bo-Un Yoon ,  Kwang-Wook Lee ,  Jeong-Nam Han

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/30604 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅极图案，并且使用第一湿蚀刻工艺蚀刻栅极图案的侧面以形成第一凹部。 第一湿蚀刻工艺包括使用含有包含羟基官能团（-OH）的第一化学物质和能够氧化底物的第二化学物质的蚀刻剂。 第二化学物质的浓度为第一化学物质浓度的1.5倍以下。

公开(公告)号：US09023704B2

公开(公告)日：2015-05-05

申请号：US13801341

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il-Young Yoon ,  Chang-Sun Hwang ,  Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon

IPC: H01L21/336 ,  H01L27/14 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.

Abstract translation: 一种制造半导体器件的方法包括形成覆盖形成在衬底上的翅片的预隔离层，所述预隔离层包括与所述翅片接触的下预分离层和不与所述翅片接触的上预隔离层 通过执行第一抛光工艺去除上部预隔离层的一部分，并且平坦化预隔离层，使得翅片的上表面和预隔离层的上表面共面，通过执行 用于去除上部预隔离层的剩余部分的第二抛光工艺。

公开(公告)号：US20130137240A1

公开(公告)日：2013-05-30

申请号：US13679345

申请日：2012-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kevin Ahn ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/30621 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76205 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545

Abstract: Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness.

Abstract translation: 提供了制造半导体器件的方法。 所述方法包括在半导体衬底上形成硬掩模图案，使用硬掩模图案作为掩模，在半导体衬底上形成具有第一宽度的第一沟槽和具有第二宽度的第二沟槽，在硬掩模上形成氧化物膜 图案和第一沟槽和第二沟槽，通过平坦化氧化膜直到硬掩模图案露出来在第一和第二沟槽上形成第一和第二隔离膜，并且通过对半导体进行干洗来蚀刻第一隔离膜第一厚度第一厚度 衬底并用不同于第一厚度的第二厚度蚀刻第二隔离膜。

公开(公告)号：US10734380B2

公开(公告)日：2020-08-04

申请号：US16158797

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US09947672B2

公开(公告)日：2018-04-17

申请号：US15371751

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20170084617A1

公开(公告)日：2017-03-23

申请号：US15371751

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US09466697B2

公开(公告)日：2016-10-11

申请号：US14721004

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Abstract translation: 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。