公开(公告)号：US20220320312A1

公开(公告)日：2022-10-06

申请号：US17568170

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomjin PARK ,  Dongwon KIM ,  Bongseok SUH ,  Daewon KIM

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes a first and second active regions extending in a first direction and having respective first and second widths in a second direction, the second width greater than the first width, a connection region connected to the first and second active regions and having a third width, between the first and second widths in the second direction, first and second gate structures respectively intersecting the first and second active regions and extending in the second direction, and a dummy structure intersecting at least a portion of the connection region, extending in the second direction, and between the first and second gate structures in the first direction. The dummy structure includes first and second pattern portions spaced apart from a side surface of the first gate structure by respective first and second distances in the first direction, the second distance greater than the first distance.

公开(公告)号：US20220157853A1

公开(公告)日：2022-05-19

申请号：US17369236

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20240355883A1

公开(公告)日：2024-10-24

申请号：US18385537

申请日：2023-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Myung Gil KANG ,  Dongwon KIM ,  Jongsu KIM ,  Beomjin PARK ,  Byeonghee SON

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0653

Abstract: A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.

公开(公告)号：US20240178293A1

公开(公告)日：2024-05-30

申请号：US18228824

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Beomjin PARK ,  Myung Gil KANG ,  Dongwon KIM ,  Younggwon KIM

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/7848

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns spaced apart from and vertically stacked on each other, a source/drain pattern connected to the semiconductor patterns having a p-type, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate dielectric layer between the gate electrode and the semiconductor patterns and including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer that extends from bottom to lateral surfaces of the outer electrode. The outer electrode and the outer gate dielectric layer have an inverted T shape.

公开(公告)号：US20240153954A1

公开(公告)日：2024-05-09

申请号：US18414039

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHOI ,  Keunhwi CHO ,  Myunggil KANG ,  Seokhoon KIM ,  Dongwon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20200235222A1

公开(公告)日：2020-07-23

申请号：US16836138

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwoo NOH ,  Munhyeon KIM ,  Hansu OH ,  Sungman WHANG ,  Dongwon KIM

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.

公开(公告)号：US20180246508A1

公开(公告)日：2018-08-30

申请号：US15908558

申请日：2018-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon CHOI ,  Sung-Dae CHO ,  Nara CHO ,  Dongwon KIM ,  Dongjin PARK ,  Sang-Min SHIN

IPC: G05D1/00

CPC classification number: G05D1/0022 ,  B60R25/24 ,  G08C17/02

Abstract: Various embodiments of the present disclosure relate to an apparatus and a method for communicating with another electronic device in an electronic device. The electronic device includes: a first communication module configured to support low frequency communication; a second communication module configured to support cellular communication; at least one sensor; at least one processor; and a memory electrically connected with the processor, wherein, when being executed, the memory may store instructions that cause the at least one processor to detect a motion of the electronic device based on the at least one sensor, and to transmit a signal for controlling an activation state regarding the low-frequency communication with another electronic device to the another electronic device via the second communication module, based on motion information of the electronic device. Other embodiments are possible.

公开(公告)号：US20130285019A1

公开(公告)日：2013-10-31

申请号：US13833987

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Dongwon KIM ,  Dae Mann Kim ,  Yoon-Ha Jeong ,  Sooyoung Park ,  Chan-Hoon Park ,  Rock-Hyun Baek ,  Sang-Hyun Lee

IPC: H01L29/775 ,  H01L29/78

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/78 ,  Y10S977/742

Abstract: Provided is a field effect transistor including a drain region, a source region, and a channel region. The field effect transistor may further include a gate electrode on or surrounding at least a portion of the channel region, and a gate dielectric layer between the channel region and the gate electrode. A portion of the channel region adjacent the source region has a sectional area smaller than that of another portion of the channel region adjacent the drain region.

Abstract translation: 提供了包括漏极区域，源极区域和沟道区域的场效应晶体管。 场效应晶体管还可以包括在沟道区的至少一部分上或围绕沟道区的至少一部分的栅电极，以及沟道区和栅电极之间的栅介质层。 与源极区域相邻的沟道区域的一部分的截面积小于与漏极区域相邻的沟道区域的另一部分的截面面积。

公开(公告)号：US20240096995A1

公开(公告)日：2024-03-21

申请号：US18231841

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Myunggil KANG ,  Dongwon KIM ,  Younggwon KIM ,  Hyumin YOO ,  Soojin JEONG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device, may include an active region extending in a first direction; a plurality of channel layers on the active region to be spaced apart from each other; a gate structure, surrounding the plurality of channel layers, respectively; and source/drain regions on the active region on at least one side of the gate structure, and contacting the plurality of channel layers, wherein the gate structure may include an upper portion on an uppermost channel layer among the plurality of channel layers and lower portions between each of the plurality of channel layers in a region vertically overlapping the plurality of channel layers, wherein a width of each of the plurality of channel layers in the first direction may be less than a width of lower portions of the gate structure, adjacent to the respective channel layers among the lower portions of the gate structure in the first direction.

公开(公告)号：US20240038763A1

公开(公告)日：2024-02-01

申请号：US18486331

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.