公开(公告)号：US10153277B2

公开(公告)日：2018-12-11

申请号：US15390361

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Gi-gwan Park ,  Ji-myoung Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8258

Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.

公开(公告)号：US10096714B2

公开(公告)日：2018-10-09

申请号：US15446322

申请日：2017-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yup Chung ,  Myung-yoon Um ,  Dong-ho Cha ,  Jung-gun You ,  Gi-gwan Park

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161

Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

公开(公告)号：US09887080B2

公开(公告)日：2018-02-06

申请号：US15372434

申请日：2016-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-hun Moon ,  Yong-suk Tak ,  Gi-gwan Park

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/02126 ,  C23C16/30 ,  C23C16/45531 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28247 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming a SiOCN material layer and a method of fabricating a semiconductor device are provided, the method of forming a SiOCN material layer including supplying a silicon source onto a substrate; supplying a carbon source onto the substrate; supplying an oxygen source onto the substrate; and supplying a nitrogen source onto the substrate, wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof.

公开(公告)号：US12015086B2

公开(公告)日：2024-06-18

申请号：US17315818

申请日：2021-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon Lee ,  Gi-gwan Park ,  Tae-young Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/155 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2006 ,  H01L29/2206 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

公开(公告)号：US10707348B2

公开(公告)日：2020-07-07

申请号：US16587227

申请日：2019-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun You ,  Gi-gwan Park ,  Ki-il Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US10483399B2

公开(公告)日：2019-11-19

申请号：US16150795

申请日：2018-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-yup Chung ,  Myung-yoon Um ,  Dong-ho Cha ,  Jung-gun You ,  Gi-gwan Park

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161

Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

公开(公告)号：US10461189B2

公开(公告)日：2019-10-29

申请号：US16028918

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun You ,  Gi-gwan Park ,  Ki-il Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US10431685B2

公开(公告)日：2019-10-01

申请号：US15404673

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hoon Lee ,  Gi-gwan Park ,  Tae-young Kim ,  Yi-young Na ,  Dae-hee Kim

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate; a gate insulating film covering a top surface and both side walls of the fin-shaped active region; a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film; one pair of insulating spacers on both side walls of the gate electrode; and a source region and a drain region on the substrate and respectively located on sides of the gate electrode. The source region and the drain region form a source/drain pair. The one pair of insulating spacers include protrusions that protrude from upper portions of the one pair of insulating spacers toward the gate electrode.

公开(公告)号：US20170222014A1

公开(公告)日：2017-08-03

申请号：US15401659

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Hyun-seung Kim ,  Bon-young Koo ,  Ki-yeon Park ,  Gi-gwan Park ,  Mi-seon Park

IPC: H01L29/49 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L29/4983 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.

公开(公告)号：US11037926B2

公开(公告)日：2021-06-15

申请号：US17014254

申请日：2020-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.