公开(公告)号：US09588570B2

公开(公告)日：2017-03-07

申请号：US14263309

申请日：2014-04-28

Applicant: Samsung Electronics Co., Ltd. ,  Wisconsin Alumni Research Foundation

Inventor： Ho-Young Kim ,  Nam-Sung Kim ,  Daniel W. Chang

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3234 ,  G06F13/4234 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method for adjusting bandwidth, a bandwidth scaler and an apparatus are provided. The method for adjusting bandwidth involves determining a dynamic context of a processor, and based on the determined dynamic context, scaling bandwidth between the processor and a memory.

Abstract translation: 提供了一种用于调整带宽的方法，带宽缩放器和装置。 用于调整带宽的方法涉及确定处理器的动态上下文，并且基于所确定的动态上下文，缩放处理器和存储器之间的带宽。

公开(公告)号：US09023704B2

公开(公告)日：2015-05-05

申请号：US13801341

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il-Young Yoon ,  Chang-Sun Hwang ,  Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon

IPC: H01L21/336 ,  H01L27/14 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.

Abstract translation: 一种制造半导体器件的方法包括形成覆盖形成在衬底上的翅片的预隔离层，所述预隔离层包括与所述翅片接触的下预分离层和不与所述翅片接触的上预隔离层 通过执行第一抛光工艺去除上部预隔离层的一部分，并且平坦化预隔离层，使得翅片的上表面和预隔离层的上表面共面，通过执行 用于去除上部预隔离层的剩余部分的第二抛光工艺。

公开(公告)号：US10480111B2

公开(公告)日：2019-11-19

申请号：US14594435

申请日：2015-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Myung-Seob Song ,  Dae Wook Park ,  Soon Cheol Kweon ,  Seung Kyung Park ,  Ho-Young Kim ,  Tae-Hong Kim ,  Junhee Choi

IPC: D06F19/00 ,  D06F35/00 ,  D06F17/10 ,  D06F37/26

Abstract: A washing machine includes a tub; a drum rotatably disposed inside the tub; and an ultrasound generator configured to emit ultrasonic waves to washing water loaded in the drum, and to generate bubbles. The ultrasound generator applies ultrasonic energy to the washing water to cause chaotic oscillation of the bubbles.

公开(公告)号：US20180358544A1

公开(公告)日：2018-12-13

申请号：US16108316

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Young Kim ,  Jin-Hye Bae ,  Hoon Han ,  Won-Jun Lee ,  Chang-Kyu Lee ,  Geun-Joo Baek ,  Jung-Ig Jeon

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A composition for cleaning a magnetic pattern, a method of manufacturing a magnetic memory device, a method of forming a magnetic pattern, and a magnetic memory device, the composition including a glycol ether-based organic solvent; a decomposing agent that includes an aliphatic amine; and at least one of a chelating agent, or a cleaning accelerator that includes an organic alkaline compound, wherein the composition is devoid of water.

公开(公告)号：US10056466B2

公开(公告)日：2018-08-21

申请号：US15191555

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jae Lee ,  Ja-Eung Koo ,  Ho-Young Kim ,  Yeong-Bong Park ,  Il-Su Park ,  Bo-Un Yoon ,  Il-Young Yoon ,  Youn-Su Ha

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

公开(公告)号：US09627542B2

公开(公告)日：2017-04-18

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.