公开(公告)号：US12142544B2

公开(公告)日：2024-11-12

申请号：US17734700

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwan Kim ,  Young-Deuk Kim ,  Jae Choon Kim ,  Kyung Suk Oh ,  Eungchang Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

公开(公告)号：US10790213B2

公开(公告)日：2020-09-29

申请号：US16139526

申请日：2018-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Choon Kim ,  Young-Deuk Kim ,  Younghoon Hyun

IPC: H01L23/367 ,  H01L29/41 ,  H01L23/00

Abstract: A heat radiation device includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A second electrode is disposed on the semiconductor substrate and is spaced apart from the first electrode. A first through electrode is disposed in the semiconductor substrate. The first through electrode is electrically connected to the first electrode.

公开(公告)号：US10347611B2

公开(公告)日：2019-07-09

申请号：US15406925

申请日：2017-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichul Kim ,  Jae Choon Kim ,  Hansung Ryu ,  KyongSoon Cho ,  YoungSang Cho ,  Yeo-Hoon Yoon

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L29/06

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

公开(公告)号：US20160197057A1

公开(公告)日：2016-07-07

申请号：US14955516

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mitsuo Umemoto ,  Donghan Kim ,  Jae Choon Kim ,  Jikho Song ,  Inho Choi

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3192 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The invention relates to a semiconductor package that includes a connection member disposed at one side of the semiconductor chip, an insulating layer covering bottom surfaces of the semiconductor chip and the connection member, a molding layer that is disposed on the insulating layer and covers a side surface of the semiconductor chip and a top surface and opposing side surfaces of the connection member, an electric line disposed on the insulating layer and electrically connected to the semiconductor chip and the connection member, and an external terminal disposed on the insulating layer and electrically connected to the electric line.

Abstract translation: 本发明涉及一种半导体封装，其包括设置在半导体芯片的一侧的连接构件，覆盖半导体芯片的底面和连接构件的绝缘层，模制层，其设置在绝缘层上并覆盖一侧 半导体芯片的表面和连接构件的顶表面和相对的侧表面，设置在绝缘层上并电连接到半导体芯片和连接构件的电线以及设置在绝缘层上并电连接的外部端子 到电线。

公开(公告)号：US20240413053A1

公开(公告)日：2024-12-12

申请号：US18410761

申请日：2024-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjoon Koh ,  Jae Choon Kim

IPC: H01L23/427 ,  H01L23/00

Abstract: Disclosed are heat radiation devices and semiconductor apparatuses including the same. The semiconductor apparatus comprises a substrate, a plurality of semiconductor devices on the substrate and arranged in a first direction as a horizontal direction, and a heat radiation device on the plurality of semiconductor devices. The heat radiation device provides a plurality of vapor chambers. The plurality of vapor chambers are spaced apart from each other in the first direction and are not connected to each other.

公开(公告)号：US12125766B2

公开(公告)日：2024-10-22

申请号：US17537689

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Hwan Kim ,  Jae Choon Kim ,  Kyung Suk Oh

IPC: H01L35/32 ,  F25B21/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/38 ,  H01L23/48 ,  H01L23/522 ,  H01L25/16

CPC classification number: H01L23/38 ,  H01L23/3121 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/16 ,  H01L24/73 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip bumps between the first package substrate and the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a molding member which covers the plurality of second semiconductor chips, on the first semiconductor chip, and a thermoelectric cooling layer attached onto a surface of the first semiconductor chip. The thermoelectric cooling layer includes a cooling material layer extending along the surface of the first semiconductor chip, a first electrode pattern which surrounds the plurality of first chip bumps from a planar viewpoint, in the cooling material layer, and a second electrode pattern which surrounds the first electrode pattern from the planar viewpoint, in the cooling material layer.

公开(公告)号：US20240119211A1

公开(公告)日：2024-04-11

申请号：US18206278

申请日：2023-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Ho Lee ,  Jae Choon Kim ,  Tae-Hyun Kim ,  Jeong-Hyeon Park ,  Hwanjoo Park ,  Sunggu Kang ,  Sung-Ho Mun

IPC: G06F30/392 ,  G06N20/00

CPC classification number: G06F30/392 ,  G06N20/00

Abstract: A semiconductor design optimization system that includes: a data base configured to store design data, a training data preprocessing unit configured to preprocess the design data and generate training data, a data learning unit configured to generate a physical property prediction model by training using the training data, a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated, and a layout generator configured generate a design layout optimized to distribute the predicted physical property values for each region of the semiconductor device to be fabricated by modifying the design drawings based on the predicted physical property data.

公开(公告)号：US11600608B2

公开(公告)日：2023-03-07

申请号：US17204225

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichul Kim ,  Chajea Jo ,  Sang-Uk Han ,  Kyoung Soon Cho ,  Jae Choon Kim ,  Woohyun Park

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/18

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US11205604B2

公开(公告)日：2021-12-21

申请号：US16148471

申请日：2018-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Choon Kim ,  Woo Hyun Park ,  Eon Soo Jang ,  Young Sang Cho

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/13 ,  H01L25/10 ,  H01L23/498

Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

公开(公告)号：US11004760B2

公开(公告)日：2021-05-11

申请号：US16752044

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Hyun Park ,  Jae Choon Kim

IPC: H01L27/146 ,  H01L23/34 ,  H01L23/31 ,  H04N5/225 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L25/065

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.