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公开(公告)号:US20210320664A1
公开(公告)日:2021-10-14
申请号:US17077891
申请日:2020-10-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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公开(公告)号:US11115021B2
公开(公告)日:2021-09-07
申请号:US17021728
申请日:2020-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tongsung Kim , Youngmin Jo , Jungjune Park , Jindo Byun , Dongho Shin , Jeongdon Ihm
IPC: H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号:US11107512B2
公开(公告)日:2021-08-31
申请号:US17001941
申请日:2020-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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14.
公开(公告)号:US11080218B2
公开(公告)日:2021-08-03
申请号:US16425105
申请日:2019-05-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Manjae Yang , Jangwoo Lee , Hwasuk Cho , Jeongdon Ihm
Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.
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15.
公开(公告)号:US09881679B2
公开(公告)日:2018-01-30
申请号:US15461241
申请日:2017-03-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jangwoo Lee , Kyoungtae Kang , Taesung Lee , Jeongdon Ihm
Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.
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公开(公告)号:US11870399B2
公开(公告)日:2024-01-09
申请号:US17227996
申请日:2021-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seunghwan Hong , Youngsoo Sohn , Jeongdon Ihm , Changhyun Bae , Yoochang Sung
CPC classification number: H03F1/26 , H03F3/19 , H03F2200/375
Abstract: A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.
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公开(公告)号:US20230027964A1
公开(公告)日:2023-01-26
申请号:US17856394
申请日:2022-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jinkwan Park , Janghoo Kim , Yoonsuk Park , Yoochang Sung , Changsik Yoo , Jeongdon Ihm
Abstract: An integrated circuit includes a T-coil formed in a first metal layer, wherein the T-coil may include: a first inductor connected to a first terminal and a second terminal; and a second inductor connected to the second terminal and a third terminal, wherein the first inductor and the second inductor may include a first pattern and a second pattern, respectively, the first and second patterns extending parallel to each other in a first direction from the second terminal in the first metal layer, and wherein the first pattern and the second pattern may form a bridge capacitor of the T-coil.
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公开(公告)号:US11562780B2
公开(公告)日:2023-01-24
申请号:US17411421
申请日:2021-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
IPC: G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号:US11522550B2
公开(公告)日:2022-12-06
申请号:US17077891
申请日:2020-10-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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公开(公告)号:US11502687B2
公开(公告)日:2022-11-15
申请号:US17389148
申请日:2021-07-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tongsung Kim , Youngmin Jo , Jungjune Park , Jindo Byun , Dongho Shin , Jeongdon Ihm
IPC: H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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