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    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT
    11.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20210320664A1

    公开(公告)日：2021-10-14

    申请号：US17077891

    申请日：2020-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: H03L7/081 ,  G11C7/22 ,  H03K5/133 ,  H03L7/085

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

    Impedance calibration circuit and memory device including the same
    12.
    发明授权
    Impedance calibration circuit and memory device including the same 有权

    公开(公告)号：US11115021B2

    公开(公告)日：2021-09-07

    申请号：US17021728

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Jungjune Park ,  Jindo Byun ,  Dongho Shin ,  Jeongdon Ihm

    IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

    Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

    Interface chip used to select memory chip and storage device including interface chip and memory chip
    14.
    发明授权
    Interface chip used to select memory chip and storage device including interface chip and memory chip 有权

    公开(公告)号：US11080218B2

    公开(公告)日：2021-08-03

    申请号：US16425105

    申请日：2019-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manjae Yang ,  Jangwoo Lee ,  Hwasuk Cho ,  Jeongdon Ihm

    IPC: G06F13/16 ,  G11C7/10 ,  G06F3/06 ,  G11C8/12 ,  G11C5/04 ,  G11C8/06 ,  G11C16/06 ,  G11C16/08

    Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

    Receiver for cancelling common mode offset and crosstalk
    16.
    发明授权
    Receiver for cancelling common mode offset and crosstalk 有权

    公开(公告)号：US11870399B2

    公开(公告)日：2024-01-09

    申请号：US17227996

    申请日：2021-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghwan Hong ,  Youngsoo Sohn ,  Jeongdon Ihm ,  Changhyun Bae ,  Yoochang Sung

    IPC: H03F1/26 ,  H03F3/19

    CPC classification number: H03F1/26 ,  H03F3/19 ,  H03F2200/375

    Abstract: A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.

    Semiconductor device including delay compensation circuit
    19.
    发明授权
    Semiconductor device including delay compensation circuit 有权

    公开(公告)号：US11522550B2

    公开(公告)日：2022-12-06

    申请号：US17077891

    申请日：2020-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: G11C7/22 ,  H03K5/133 ,  H03L7/081 ,  H03L7/085 ,  G11C29/02

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

    Impedance calibration circuit and memory device including the same
    20.
    发明授权
    Impedance calibration circuit and memory device including the same 有权

    公开(公告)号：US11502687B2

    公开(公告)日：2022-11-15

    申请号：US17389148

    申请日：2021-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Jungjune Park ,  Jindo Byun ,  Dongho Shin ,  Jeongdon Ihm

    IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

    Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

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