公开(公告)号：US20130330881A1

公开(公告)日：2013-12-12

申请号：US13772427

申请日：2013-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Woo PARK ,  Seok-Hyun LEE ,  Ho-Geon SONG

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Abstract translation: 提供双面胶带，半导体封装以及制造封装的方法。 制造半导体封装的方法包括在载体的顶表面上提供双面胶带，所述双面胶带包括第一粘合剂层和层叠在第一粘合剂层上的第二粘合剂层，第一粘合剂层 所述双面胶带与所述载体的顶表面接触，将多个半导体芯片的活性表面粘合到所述双面胶带的第二粘合剂层上，从而将所述第一粘合剂层与所​​述第二粘合层分离， 第二粘合剂层保留在半导体芯片的有效表面上，图案化第二粘合剂层以形成选择性地暴露半导体芯片的有效表面的第一开口，以及在第二粘合剂层上形成第一导电部件以填充第一开口 。

公开(公告)号：US20240072000A1

公开(公告)日：2024-02-29

申请号：US18455922

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo PARK ,  Un-Byoung KANG ,  Chung Sun LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L25/0655 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/182

Abstract: A semiconductor package includes a substrate; a substrate pad on the substrate; a first semiconductor chip and a second semiconductor chip on the substrate; a connective terminal between the substrate pad and the first semiconductor chip and between the substrate pad and the second semiconductor chip; a dummy pad on the substrate, and spaced apart from the substrate pad, wherein the dummy pad is between the first semiconductor chip and the second semiconductor chip; and an underfill material layer interposed between the substrate and the first semiconductor chip and between the substrate and the second semiconductor chip, wherein the dummy pad and the substrate pad include a same material.

公开(公告)号：US20220216068A1

公开(公告)日：2022-07-07

申请号：US17656695

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho PARK ,  Jin-Woo PARK ,  Seok Hyun LEE ,  Jae Gwon JANG ,  Gwang Jae JEON

IPC: H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method for fabricating a semiconductor package, the method including: forming a. release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

公开(公告)号：US20200052427A1

公开(公告)日：2020-02-13

申请号：US16499378

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd. ,  Hyupjinconnector Co., Ltd.

Inventor： Sung-Hyup LEE ,  Jae-Woon LEE ,  Yong-Seok LEE ,  Yang-Jean PARK ,  Jin-Woo PARK

IPC: H01R13/24 ,  H01R13/46

Abstract: A multi-connection device according to various embodiments of the present invention may comprise: a housing; and a first or a second connection terminal for electrical connection, the first and second connection terminals protruding in first and second directions from the housing, respectively. Various other embodiments may also be possible.

公开(公告)号：US20160154119A1

公开(公告)日：2016-06-02

申请号：US14953064

申请日：2015-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Ik KIM ,  Jin-Woo PARK ,  Eun Jeong JO

IPC: G01T1/20

CPC classification number: G03B42/025 ,  G01T1/2018 ,  G01T1/244

Abstract: Disclosed herein is an X-ray imaging apparatus having an improved structure which is configured for preventing an entrance of foreign materials. The X-ray imaging apparatus includes: an X-ray source configured to generate X-rays, and to irradiate the generated X-rays; an X-ray detector configured to detect the irradiated X-rays; and a first frame and a second frame coupled with each other to form an outer appearance of the X-ray detector. The first frame is tightly coupled with the second frame so that no gap exists between the first frame and the second frame in order to prevent a foreign material from entering the inside of the X-ray detector.

Abstract translation: 这里公开了具有改进的结构的X射线成像装置，其被配置为防止异物进入。 X射线成像装置包括：X射线源，其被配置为产生X射线，并照射生成的X射线; 被配置为检测所照射的X射线的X射线检测器; 以及彼此联接以形成X射线检测器的外观的第一框架和第二框架。 第一框架与第二框架紧密耦合，使得在第一框架和第二框架之间不存在间隙，以防止异物进入X射线检测器的内部。

公开(公告)号：US20140256089A1

公开(公告)日：2014-09-11

申请号：US14286454

申请日：2014-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Bin YIM ,  Seung-Kon MOK ,  Jin-Woo PARK ,  Dae-Young CHOI ,  Mi-Yeon KIM

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.

Abstract translation: 半导体封装包括第一半导体封装，包括第一印刷电路板和安装在第一印刷电路板上的第一半导体器件，以及堆叠在第一半导体封装上的第二半导体封装，并且包括第二印刷电路板和第二半导体 装置安装在第二印刷电路板上。 半导体封装包括至少一个第一通孔，其通过第一半导体器件将第二半导体封装电连接到第一印刷电路板。

公开(公告)号：US20130147063A1

公开(公告)日：2013-06-13

申请号：US13626012

申请日：2012-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo PARK ,  Hogeon SONG ,  Seokhyun LEE

IPC: H01L25/07

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/055 ,  H01L23/057 ,  H01L23/08 ,  H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/4926 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip.

Abstract translation: 扇出晶片级封装可以包括至少两个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。 再分布线图案可以电连接到至少两个半导体芯片。 外部端子可以电连接到再分配线图案。 扇出晶片级封装可以包括至少三个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。

公开(公告)号：US20240178188A1

公开(公告)日：2024-05-30

申请号：US18363140

申请日：2023-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung-Sung KANG ,  Kyong Hwan KOH ,  Jin-Woo PARK ,  Chung Sun LEE ,  Hyeon Jun JIN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/182

Abstract: Semiconductor packages and methods of fabricating the same are provided. The semiconductor package includes a first package substrate including a first area, a first semiconductor chip mounted on the first area, a second package substrate disposed on an upper surface of the first semiconductor chip and including a second area and a first hole penetrating through the second area, a second semiconductor chip mounted on the second area, a connection member electrically connecting the first package substrate and the second package substrate and between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.

公开(公告)号：US20210257223A1

公开(公告)日：2021-08-19

申请号：US17037003

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho PARK ,  Jin-Woo PARK ,  Seok Hyun LEE ,  Jae Gwon JANG ,  Gwang Jae JEON

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00

Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

公开(公告)号：US20210057317A1

公开(公告)日：2021-02-25

申请号：US16819318

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho PARK ,  Da Hye KIM ,  Jin-Woo PARK ,  Jae Gwon JANG

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.