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公开(公告)号:US09929235B1
公开(公告)日:2018-03-27
申请号:US15463551
申请日:2017-03-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Dong Il Bae , Chang Woo Sohn , Seung Min Song , Dong Hun Lee
IPC: H01L29/76 , H01L29/06 , H01L29/423 , H01L27/088 , H01L27/02 , H01L27/092 , H01L29/10 , H01L29/165 , H01L21/8234 , H01L21/8238 , H01L29/08 , H01L29/66
CPC classification number: H01L29/0673 , H01L21/823431 , H01L21/823456 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L27/0207 , H01L27/0883 , H01L27/0886 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L29/0669 , H01L29/0847 , H01L29/1033 , H01L29/165 , H01L29/42392 , H01L29/66545 , H01L29/785
Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
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公开(公告)号:US11908952B2
公开(公告)日:2024-02-20
申请号:US17840737
申请日:2022-06-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Woo Seok Park , Dong Chan Suh , Seung Min Song , Geum Jong Bae , Dong Il Bae
IPC: H01L29/786 , H01L29/423 , H01L29/10 , H01L29/161 , H01L29/08 , H01L29/66 , H01L29/775 , B82Y10/00 , H01L29/06
CPC classification number: H01L29/78696 , B82Y10/00 , H01L29/0673 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78618
Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
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公开(公告)号:US11107822B2
公开(公告)日:2021-08-31
申请号:US16722081
申请日:2019-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Sun Wook Kim , Jun Beom Park , Tae Young Kim , Geum Jong Bae
IPC: H01L27/11 , H01L23/528 , H01L29/06 , H01L29/775 , H01L27/02 , H01L29/423 , H01L29/78
Abstract: A semiconductor device includes first and second fin type patterns, first and second gate patterns intersecting the first and second fin type patterns, third and fourth gate patterns intersecting the first fin type pattern between the first and the second gate patterns, a fifth gate pattern intersecting the second fin type pattern, a sixth gate pattern intersecting the second fin type pattern, first to third semiconductor patterns disposed among the first, the third, the fourth and the second gate patterns, and fourth to sixth semiconductor patterns disposed among the first, the fifth, the sixth and the second gate patterns. The first semiconductor pattern to the fourth semiconductor pattern and the sixth semiconductor pattern are electrically connected to a wiring structure, and the fifth semiconductor pattern is not connected to the wiring structure.
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公开(公告)号:US20210091232A1
公开(公告)日:2021-03-25
申请号:US16953785
申请日:2020-11-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Woo Seok Park , Dong Chan Suh , Seung Min Song , Geum Jong Bae , Dong Il Bae
IPC: H01L29/786 , H01L29/423 , H01L29/10 , H01L29/161 , H01L29/08 , H01L29/66 , H01L29/775 , B82Y10/00 , H01L29/06
Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
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公开(公告)号:US10665723B2
公开(公告)日:2020-05-26
申请号:US16161765
申请日:2018-10-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seung Min Song , Woo Seok Park , Geum Jong Bae , Dong Il Bae , Jung Gil Yang
IPC: H01L29/66 , H01L29/786 , H01L29/06 , H01L29/423 , H01L21/02
Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.
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公开(公告)号:US10347718B2
公开(公告)日:2019-07-09
申请号:US15877667
申请日:2018-01-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Dong Il Bae , Chang Woo Sohn , Seung Min Song , Dong Hun Lee
IPC: H01L21/70 , H01L29/06 , H01L29/66 , H01L29/08 , H01L21/8238 , H01L21/8234 , H01L27/088 , H01L29/165 , H01L29/10 , H01L27/092 , H01L27/02 , H01L29/423 , H01L29/78
Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
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公开(公告)号:US12107135B2
公开(公告)日:2024-10-01
申请号:US17467660
申请日:2021-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Seung Min Song , Soo Jin Jeong , Dong Il Bae , Bong Seok Suh
IPC: H01L29/423 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786
CPC classification number: H01L29/42392 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0642 , H01L29/4983 , H01L29/51 , H01L29/785 , H01L29/7851 , H01L29/78696
Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.
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公开(公告)号:US11710741B2
公开(公告)日:2023-07-25
申请号:US17243943
申请日:2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Woo Noh , Myung Gil Kang , Geum Jong Bae , Dong Il Bae , Jung Gil Yang , Sang Hoon Lee
IPC: H01L27/092 , H01L29/78 , H01L29/66 , H01L21/033 , H01L21/8238 , H01L29/10 , H01L29/08
CPC classification number: H01L27/0924 , H01L21/0337 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/0847 , H01L29/1033 , H01L29/6656 , H01L29/6681 , H01L29/66545 , H01L29/785 , H01L2029/7858
Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.
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公开(公告)号:US11640973B2
公开(公告)日:2023-05-02
申请号:US17508197
申请日:2021-10-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Dong Il Bae , Chang Woo Sohn , Seung Min Song , Dong Hun Lee
IPC: H01L29/06 , H01L21/8234 , H01L29/66 , H01L29/08 , H01L21/8238 , H01L27/088 , H01L29/165 , H01L29/10 , H01L27/092 , H01L27/02 , H01L29/423 , H01L29/78 , H01L29/786
Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
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公开(公告)号:US11164943B2
公开(公告)日:2021-11-02
申请号:US16928439
申请日:2020-07-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Dong Il Bae , Chang Woo Sohn , Seung Min Song , Dong Hun Lee
IPC: H01L29/06 , H01L29/66 , H01L29/08 , H01L21/8238 , H01L21/8234 , H01L27/088 , H01L29/165 , H01L29/10 , H01L27/092 , H01L27/02 , H01L29/423 , H01L29/78 , H01L29/786
Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
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