公开(公告)号：US20170200675A1

公开(公告)日：2017-07-13

申请号：US15403480

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung JUNG ,  Kwangjin MOON ,  Byung Lyul PARK ,  Jin Ho AN

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76826 ,  H01L21/76886 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2225/06544 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.

公开(公告)号：US20240071841A1

公开(公告)日：2024-02-29

申请号：US18302401

申请日：2023-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin PARK ,  Taeseong KIM ,  Jaehyung PARK ,  Kyuha LEE ,  Yeojin LEE ,  Kwangjin MOON ,  Hojin LEE

IPC: H01L21/66 ,  B24B37/013 ,  G06F30/392 ,  H01L23/00

CPC classification number: H01L22/20 ,  B24B37/013 ,  G06F30/392 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03845 ,  H01L2224/05571 ,  H01L2224/05647

Abstract: In a manufacturing method of a wafer, the method including: an operation of preparing a wafer including a semiconductor chip region and a test region, measuring a measurement region included in the test region with an atomic force microscope (AFM), the measurement region including a plurality of metal lines having a constant line width and a constant pitch; determining a surface roughness value of the test region based on a result of the measuring of the measurement region; determining a step difference value of the metal lines of the test region based on the surface roughness value; and determining a step difference value of bonding pads in the semiconductor chip region based on the step difference value of the metal lines.

公开(公告)号：US20220223555A1

公开(公告)日：2022-07-14

申请号：US17709856

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun JEON ,  Kwangjin MOON ,  Hakseung LEE ,  Hyoukyung CHO

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.

公开(公告)号：US20220093567A1

公开(公告)日：2022-03-24

申请号：US17376784

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

公开(公告)号：US20210305130A1

公开(公告)日：2021-09-30

申请号：US17036145

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohye CHO ,  Pilkyu KANG ,  Kwangjin MOON ,  Taeseong KIM

IPC: H01L23/48 ,  H01L23/528 ,  H01L27/11 ,  H01L21/768

Abstract: An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

公开(公告)号：US20210233879A1

公开(公告)日：2021-07-29

申请号：US17229023

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kwangjin MOON ,  Sujeong PARK ,  JuBin SEO ,  Jin Ho AN ,  Dong-chan LIM ,  Atsushi FUJISAKI

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US20240312935A1

公开(公告)日：2024-09-19

申请号：US18467199

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hee JANG ,  Kwangjin MOON ,  Seokho KIM ,  Soonwook KIM ,  Kunsang PARK

IPC: H01L23/00 ,  H10B80/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A bonding semiconductor device according to at least one embodiment is formed by bonding a first chip and a second chip, and includes a chip region and a partition region. A bonding pad formed by bonding a first bonding pad of the first chip and a second bonding pad of the second chip may be provided in the chip region. A separation pattern portion in which a first base layer of a first pattern portion of the first chip and a second base layer of a second pattern portion of the second chip are entirely separated from each other to have an inner space may be provided in the partition region.

公开(公告)号：US20230361004A1

公开(公告)日：2023-11-09

申请号：US18354068

申请日：2023-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan HWANG ,  Taeseong KIM ,  Hoonjoo NA ,  Kwangjin MOON ,  Hyungjun JEON

IPC: H01L23/48 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L27/0886 ,  H01L25/0657 ,  H01L21/76898 ,  H01L23/528 ,  H01L2224/0603 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L24/06

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US20230253293A1

公开(公告)日：2023-08-10

申请号：US18075535

申请日：2022-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohye CHO ,  Kwangjin MOON ,  Hojin LEE

IPC: H01L23/48 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L23/481 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device includes a first semiconductor substrate having a protruding active pattern, a gate structure, a source/drain region in the active pattern on a side of the gate structure, an interlayer insulating layer on the source/drain region, a contact structure connected to the source/drain region through the interlayer insulating layer, a through-via structure electrically connected to the contact structure and passing through the interlayer insulating layer and the first semiconductor substrate, a first bonding structure including a first insulating layer on the first semiconductor substrate and a first connection pad in the first insulating layer, a second bonding structure on the first bonding structure and including a second insulating layer bonded to the first insulating layer and a second connection pad in the second insulating layer and bonded to the first connection pad, and a second semiconductor substrate disposed on the second bonding structure.

公开(公告)号：US20230178533A1

公开(公告)日：2023-06-08

申请号：US17891629

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun JEON ,  Kwangjin MOON

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L23/3157 ,  H01L24/05 ,  H01L23/481 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/80379

Abstract: A semiconductor package includes a first semiconductor chip including first pads and a first insulating layer, and a second semiconductor chip including second upper pads, a second insulating layer, second lower pads, and through electrodes connecting the second upper pads and the second lower pads to each other. The package includes a third semiconductor chip including third upper pads, an upper barrier layer, a third insulating layer, third lower pads, a lower barrier layer, and dummy electrode structures connecting the third upper pads and the third lower pads to each other. The package includes an encapsulant below the first semiconductor chip to seal at least a portion of each of the second and third semiconductor chips and cover side surfaces of the third lower pads. The package includes bump structures below the encapsulant and the second and third semiconductor chips.