公开(公告)号：US20180248018A1

公开(公告)日：2018-08-30

申请号：US15664226

申请日：2017-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Changhee Kim ,  Yunil Lee ,  Mirco Cantoro ,  Junggun You ,  Donghun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L29/66666 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/66553 ,  H01L29/7827

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

公开(公告)号：US11488956B2

公开(公告)日：2022-11-01

申请号：US17313570

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/10 ,  H01L27/108 ,  G11C11/402

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

公开(公告)号：US11411111B2

公开(公告)日：2022-08-09

申请号：US16923389

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yeoncheol Heo

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/8258

Abstract: The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

公开(公告)号：US10418448B2

公开(公告)日：2019-09-17

申请号：US15591405

申请日：2017-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L29/267 ,  H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/06

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

公开(公告)号：US10014300B2

公开(公告)日：2018-07-03

申请号：US15480669

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Tae-yong Kwon ,  Jae-young Park ,  Dong-hoon Hwang ,  Han-ki Lee ,  So-ra You

IPC: H01L29/00 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7854

Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.

公开(公告)号：US09953883B2

公开(公告)日：2018-04-24

申请号：US15415012

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Maria Toledano Luque ,  Yeoncheol Heo ,  Dong Il Bae

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US20170243942A1

公开(公告)日：2017-08-24

申请号：US15591405

申请日：2017-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L29/267 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

公开(公告)号：US10937700B2

公开(公告)日：2021-03-02

申请号：US15583167

申请日：2017-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yun-Il Lee ,  Hyung-Suk Lee ,  Yeon-Cheol Heo ,  Byoung-Gi Kim ,  Chang-Min Yoe ,  Seung-Chan Yun ,  Dong-Hun Lee

IPC: H01L27/082 ,  H01L27/24 ,  H01L27/115 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L29/786 ,  H01L27/088 ,  H01L29/161 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78

Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.

公开(公告)号：US10896951B2

公开(公告)日：2021-01-19

申请号：US16545906

申请日：2019-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-bin Song ,  Hei-seung Kim ,  Mirco Cantoro ,  Sang-woo Lee ,  Min-hee Cho ,  Beom-yong Hwang

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/22

Abstract: A semiconductor device includes a channel layer located on a substrate, the channel layer including a conductive oxide, a gate structure located on the channel layer, the gate structure including a gate electrode and gate spacers located on both sidewalls of the gate electrode, and source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer. The source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.

公开(公告)号：US10453756B2

公开(公告)日：2019-10-22

申请号：US15937037

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Maria Toledano Luque ,  Yeoncheol Heo ,  Dong Il Bae

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/161 ,  H01L29/417

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.