公开(公告)号：US20190139811A1

公开(公告)日：2019-05-09

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20230317860A1

公开(公告)日：2023-10-05

申请号：US18207274

申请日：2023-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun LEE ,  Dong Woo KIM ,  Dong Chan SUH ,  Sun Jung KIM

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/823807 ,  H01L29/66545 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/42364 ,  H01L29/66439 ,  H01L29/0653 ,  H01L29/0847 ,  H01L27/092 ,  H01L29/66742 ,  H01L29/78684 ,  H01L29/78651 ,  Y10S977/762 ,  H01L29/068 ,  Y10S977/938 ,  Y10S977/765

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US20220190112A1

公开(公告)日：2022-06-16

申请号：US17686700

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Hee CHOI ,  Seokhoon KIM ,  Choeun LEE ,  Edward Namkyu CHO ,  Seung Hun LEE

IPC: H01L29/08 ,  H01L27/11 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/108

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

公开(公告)号：US20220130982A1

公开(公告)日：2022-04-28

申请号：US17571694

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Seung Hun LEE ,  Yang XU

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/201 ,  H01L29/20

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

公开(公告)号：US20220123145A1

公开(公告)日：2022-04-21

申请号：US17565650

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Da Hye KIM ,  Jae Mun KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Kyung In CHOI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

公开(公告)号：US20220102497A1

公开(公告)日：2022-03-31

申请号：US17546326

申请日：2021-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Seung Hun LEE ,  Su Jin JUNG ,  Young Dae CHO

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

公开(公告)号：US20200152740A1

公开(公告)日：2020-05-14

申请号：US16386459

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Seung Hun LEE ,  Su Jin JUNG ,  Young Dae CHO

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/167

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

公开(公告)号：US20190267494A1

公开(公告)日：2019-08-29

申请号：US16254842

申请日：2019-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Hyoung Sub KIM ,  Seong Heum CHOI ,  Jin Yong KIM ,  Tae Jin PARK ,  Seung Hun LEE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/30 ,  H01L29/66

Abstract: A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.

公开(公告)号：US20170092547A1

公开(公告)日：2017-03-30

申请号：US15234170

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poren Tang ,  Sunjung Steve KIM ,  Moon Seung YANG ,  Seung Hun LEE ,  Hyun Jung LEE ,  Geun Hee JEONG

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/78

Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.

公开(公告)号：US20150341124A1

公开(公告)日：2015-11-26

申请号：US14716060

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Gyu LEE ,  Seung Hun LEE ,  Young Hwan HONG

IPC: H04B10/80 ,  D06F37/30 ,  D06F33/02

CPC classification number: H04B10/802 ,  D06F23/04 ,  D06F33/02 ,  D06F37/30 ,  D06F37/304

Abstract: An asynchronous receiver-transmitter circuit which compensates for an output signal so as to be the same as an input signal upon an asynchronous communication, and a washing machine including the same. The asynchronous receiver-transmitter circuit includes a photo-coupler turned on by an applied input signal to provide an output signal; and a compensation part configured to compensate for a time required while the output signal arrives at a high value to correspond to a time required while the output signal arrives at a low value.

Abstract translation: 异步接收机 - 发射机电路，其在异步通信时补偿与输入信号相同的输出信号，以及包括该异步通信的洗衣机。 异步接收机 - 发射机电路包括通过施加的输入信号导通的光耦合器，以提供输出信号; 以及补偿部件，被配置为在输出信号到达高值时对所需的时间进行补偿，以对应于输出信号到达低值所需的时间。