公开(公告)号：US20240194648A1

公开(公告)日：2024-06-13

申请号：US18533800

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dawoon Jung ,  Seungduk Baek ,  Donghun Lee

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/3511

Abstract: A semiconductor package includes a base structure and a plurality of semiconductor chips disposed on the base structure. Each of the plurality of semiconductor chips has a chip region. The plurality of semiconductor chips are stacked in a vertical direction such that chip regions at least partially overlap each other. In the stack of the plurality of semiconductor chips, each of the plurality of semiconductor chips has a first width in a first direction and a second width in a second direction. The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, having scribe regions on opposite sides of each of the chip regions. A first width of the first semiconductor chip is greater than a first width of the second semiconductor chip.

公开(公告)号：US20230223374A1

公开(公告)日：2023-07-13

申请号：US18185702

申请日：2023-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae CHO ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L25/0655 ,  H01L24/05 ,  H01L24/29 ,  H01L24/13 ,  H01L2224/29009 ,  H01L2224/13083 ,  H01L2224/0557 ,  H01L2224/29008 ,  H01L2924/14 ,  H01L2224/0401

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US11640951B2

公开(公告)日：2023-05-02

申请号：US16846616

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae Cho ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US11495576B2

公开(公告)日：2022-11-08

申请号：US16822693

申请日：2020-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungsoo Kim ,  Sunwon Kang ,  Seungduk Baek ,  Ho Geon Song ,  Kyung Suk Oh

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

公开(公告)号：US20250069972A1

公开(公告)日：2025-02-27

申请号：US18658652

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haseob Seong ,  Seungduk Baek ,  Aenee Jang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: Provided is a semiconductor package including a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips each including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, and a package molding layer including a bottom molding portion on a portion of an upper surface of the first semiconductor chip, which is exposed by the lowermost second semiconductor chip, and a side molding portion on side walls of the plurality of second semiconductor chips, wherein the side molding portion of the package molding layer extends in a vertical direction from an edge of an upper surface of the bottom molding portion of the package molding layer.

公开(公告)号：US12125753B2

公开(公告)日：2024-10-22

申请号：US17584776

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyeong Kim ,  Hyeongmun Kang ,  Seungduk Baek

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L22/34 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/1412 ,  H01L2224/14515 ,  H01L2224/16148 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/17515 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

公开(公告)号：US11721601B2

公开(公告)日：2023-08-08

申请号：US17095210

申请日：2020-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongmun Kang ,  Jungmin Ko ,  Seungduk Baek ,  Taehyeong Kim ,  Insup Shin

IPC: H01L23/24 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/24 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/13 ,  H01L2924/1434 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.

公开(公告)号：US09646895B2

公开(公告)日：2017-05-09

申请号：US14714667

申请日：2015-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungduk Baek ,  Ji Hwang Kim ,  Taeje Cho

IPC: H01L21/66 ,  G01R31/26 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/32 ,  H01L23/5256 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern.

公开(公告)号：US20240153898A1

公开(公告)日：2024-05-09

申请号：US18387656

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Minseung JI ,  Seungduk Baek ,  Aenee Jang

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06152 ,  H01L2224/06181 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565

Abstract: A semiconductor package includes a lower chip including a first lower bonding pad and a second lower bonding pad, and an upper chip disposed on the lower chip, the upper chip including a first upper bonding pad and a second upper bonding pad respectively hybrid-bonded together. The first lower and upper bonding pads have a first shape in which first and second axis lengths are the same, and are disposed in a first center region of the chips. The second lower and upper bonding pads have a second shape in which third and fourth axis lengths differ, and are disposed in a first edge region which is near a corner point of the chip. In the second lower and upper bonding pads disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

公开(公告)号：US20230163089A1

公开(公告)日：2023-05-25

申请号：US17934298

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minki Kim ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0652 ,  H01L23/481 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/08225 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.