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    Integrated circuit device including vertical memory
    11.
    发明授权
    Integrated circuit device including vertical memory 有权

    公开(公告)号：US11295815B2

    公开(公告)日：2022-04-05

    申请号：US16781986

    申请日：2020-02-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwanyong Kim ,  Sunil Shim ,  Wonseok Cho

    IPC: G11C16/08 ,  G11C16/04

    Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.

    Integrated circuit device including vertical memory
    16.
    发明授权
    Integrated circuit device including vertical memory 有权

    公开(公告)号：US12125535B2

    公开(公告)日：2024-10-22

    申请号：US17698627

    申请日：2022-03-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwanyong Kim ,  Sunil Shim ,  Wonseok Cho

    IPC: G11C16/08 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C16/0466 ,  G11C16/0483

    Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.

    Semiconductor device and method of fabricating the same
    19.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US10790299B2

    公开(公告)日：2020-09-29

    申请号：US16282701

    申请日：2019-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunil Shim

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/56 ,  H01L27/11573

    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises forming on a substrate a mold structure including a plurality of sacrificial patterns and a plurality of dielectric patterns that are alternately stacked, patterning the mold structure to form a plurality of preliminary stack structures extending in a first direction, forming on the preliminary stack structures a support pattern that extends in a direction intersecting the first direction and extends across the preliminary stack structures, and replacing the sacrificial patterns with conductive patterns to form a plurality of stack structures from the preliminary stack structures. The support pattern remains on the stack structures.

    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells
    20.
    发明授权
    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells 有权
    包括接地选择晶体管和第一和第二虚拟存储器单元的非易失性存储器件的操作方法

    公开(公告)号：US09548123B2

    公开(公告)日：2017-01-17

    申请号：US14820703

    申请日：2015-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byeong-In Choe ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim ,  Woonkyung Lee

    IPC: G11C16/00 ,  G11C7/00 ,  H01L29/00 ,  H01L27/11 ,  G11C16/14 ,  G11C7/14 ,  G11C16/04 ,  G11C16/30 ,  H01L29/792 ,  H01L27/115 ,  G11C16/10 ,  G11C16/16

    CPC classification number: G11C16/14 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    Abstract: A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

    Abstract translation: 非易失性存储器件包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。 所述方法可以包括将字线擦除电压施加到连接到所述单元串的存储单元的字线; 连接到单元串的地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

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