公开(公告)号：US20160141282A1

公开(公告)日：2016-05-19

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L21/321

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

Abstract translation: 在基板上形成第一绝缘层。 在第一绝缘层中形成开口。 阻挡层形成在第一绝缘层上并与开口中的第一绝缘层的侧壁一致，并且在阻挡层上形成导电层。 执行化学机械抛光以露出第一绝缘层并在开口中留下阻挡层图案，并且在开口中的阻挡层图案上具有导电层图案，其中导电层图案的一部分突出于绝缘体的上表面上方 层和阻挡层图案的上表面。 在第一绝缘层，阻挡层图案和导电层图案上形成第二绝缘层，并平坦化以暴露导电层图案。 第二衬底可以结合到暴露的导电层图案。

公开(公告)号：US09287251B2

公开(公告)日：2016-03-15

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate. A plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构。 在其上分别具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺。 第一和第二导电图案结构彼此接触以接合第一和第二基板。

公开(公告)号：US20160020197A1

公开(公告)日：2016-01-21

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate, plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构，在其上具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺， ， 分别。 第一和第二导电图案结构彼此接触以接合第一和第二基板。

公开(公告)号：US20140048952A1

公开(公告)日：2014-02-20

申请号：US13943828

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Ho-Jin Lee ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC: H01L23/538 ,  H01L23/485

CPC classification number: H01L23/5384 ,  H01L21/6836 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract translation: 提供了包括通孔结构和再分配结构的半导体器件。 半导体器件可以包括在衬底的第一侧上的内部电路，垂直穿过衬底以与内部电路中的一个电连接的通孔结构，在衬底的第二侧上的再分配结构，并且电连接到通孔 通孔结构，以及在基板的第二面和再分布结构之间的绝缘层。 再分布结构可以包括再分配阻挡层和再分布金属层，再分布阻挡层可以在再分布金属层的底表面上延伸并且可以部分地围绕再分布金属层的一侧。