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    MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SYSTEM
    12.
    发明申请
    MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SYSTEM 有权

    公开(公告)号：US20250078888A1

    公开(公告)日：2025-03-06

    申请号：US18791722

    申请日：2024-08-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tongsung Kim ,  Woojung Kim ,  Seonkyoo Lee

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A memory device correcting a data strobe signal when performing a write operation includes a correction circuit configured to receive the data strobe signal and to generate a reference delay for the received data strobe signal, and a main circuit configured to correct the data strobe signal based on the reference delay generated by the correction circuit. The correction circuit includes a delay cell configured to generate a reference delay for the data strobe signal received by the main circuit and to store the generated reference delay, when a data signal is input to the main circuit, a first counter configured to adjust the reference delay, and a second counter configured to determine a delay of the data strobe signal received by the main circuit, when a write operation is performed.

    Memory package, semiconductor device, and storage device
    16.
    发明授权
    Memory package, semiconductor device, and storage device 有权

    公开(公告)号：US11736098B2

    公开(公告)日：2023-08-22

    申请号：US17866517

    申请日：2022-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

    IPC: H03K5/14 ,  H03L7/081 ,  H03K5/135 ,  H03K5/00

    CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

    Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY DEVICE
    19.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20250095755A1

    公开(公告)日：2025-03-20

    申请号：US18932736

    申请日：2024-10-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

    IPC: G11C16/32 ,  G11C16/04 ,  G11C29/02

    Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal from the memory controller, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously.

    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY DEVICE
    20.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20250095754A1

    公开(公告)日：2025-03-20

    申请号：US18804617

    申请日：2024-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

    IPC: G11C16/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K5/156

    Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation.

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