公开(公告)号：US11508420B2

公开(公告)日：2022-11-22

申请号：US17355765

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  Daesik Moon ,  Young-Soo Sohn ,  Young-Hoon Son ,  Ki-Seok Oh ,  Changkyo Lee ,  Hyun-Yoon Cho ,  Kyung-Soo Ha ,  Seokhun Hyun

IPC: G11C7/10 ,  G06F3/06 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US10885950B2

公开(公告)日：2021-01-05

申请号：US16363077

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US09264039B2

公开(公告)日：2016-02-16

申请号：US14202323

申请日：2014-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Seok Seol ,  Seung-Jun Bae ,  Young-Soo Sohn ,  Ho-Sung Song

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00

CPC classification number: H03K19/0005

Abstract: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.

Abstract translation: 片上终端（ODT）电路包括校准单元，偏移码生成单元，加法器和ODT单元。 校准单元生成一个上拉代码和一个下拉代码。 偏移码基于模式寄存器设置信号，上拉代码和下拉码产生上拉偏移码和下拉偏移码。 加法器分别将上拉偏移代码和下拉偏移代码加到上拉代码和下拉代码，并产生一个上拉校准代码和一个下拉校准代码。 ODT单元根据上拉校准代码和下拉校准代码改变ODT电阻。

公开(公告)号：US20230066632A1

公开(公告)日：2023-03-02

申请号：US18047614

申请日：2022-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  Daesik Moon ,  Young-Soo Sohn ,  Young-Hoon Son ,  Ki-Seok Oh ,  Changkyo Lee ,  Hyun-Yoon Cho ,  Kyung-Soo Ha ,  Seokhun Hyun

IPC: G11C7/10 ,  G06F3/06 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US11049584B2

公开(公告)日：2021-06-29

申请号：US16574808

申请日：2019-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Heung Kim ,  Kyo-Min Sohn ,  Young-Soo Sohn

IPC: G11C29/38 ,  H01L25/065 ,  G11C29/12 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/56 ,  G11C29/02 ,  G11C29/50

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

公开(公告)号：US09824755B2

公开(公告)日：2017-11-21

申请号：US14465995

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Kwang-Il Park ,  Hak-Soo Yu

IPC: G06F12/10 ,  G11C14/00 ,  G11C29/00 ,  G11C11/40 ,  G11C29/44

CPC classification number: G11C14/0018 ,  G11C11/40 ,  G11C29/702 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

公开(公告)号：US09711205B2

公开(公告)日：2017-07-18

申请号：US14874568

申请日：2015-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Chul-Woo Park ,  Young-Soo Sohn

IPC: G11C11/406 ,  G06F12/02 ,  G11C11/00 ,  G11C29/28 ,  G11C29/04 ,  G11C29/44

CPC classification number: G11C11/40615 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/005 ,  G11C29/28 ,  G11C2029/0409 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

公开(公告)号：US09390778B2

公开(公告)日：2016-07-12

申请号：US14798164

申请日：2015-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-A Kim ,  Dae-Sun Kim ,  Dae-Jeong Kim ,  Sung-Min Ryu ,  Kwang-Il Park ,  Chul-Woo Park ,  Young-Soo Sohn ,  Jae-Youn Youn

IPC: G11C8/12 ,  G11C8/08 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4097

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract translation: 半导体存储器件包括存储单元阵列，子字线驱动器和功率选择开关。 存储单元阵列包括耦合到字线的存储单元行。 子字线驱动器耦合到字线。 功率选择开关耦合到子字线驱动器。 每个电源选择开关控制从字线激活的第一字线的去激活电压电平和与第一字线相邻的第二字线的截止电压电平，使得去激活电压电平和截止电压电平 具有接地电压，第一负电压和第二负电压中的至少一个。 接地电压，第一负电压和第二负电压彼此具有不同的电压电平。

公开(公告)号：US09355703B2

公开(公告)日：2016-05-31

申请号：US14077187

申请日：2013-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Jin Lee ,  Dae-Hyun Kim ,  Sang-Yun Kim ,  Jae-Sung Kim ,  Young-Soo Sohn

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C11/40611 ,  G11C11/40622 ,  G11C29/028 ,  G11C29/50016

Abstract: A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation.

Abstract translation: 刷新地址生成器可以包括查找表，其包括存储与第一数据保留时间相关联的第一组地址的第一部分，以及存储与第二数据保留时间相关联的第二组地址的第二部分，该第二组地址与第一数据保留不同 时间，其中第一部分的地址比第二部分的地址更频繁地访问以刷新对应于地址的存储单元。 系统和方法也可以实现这种刷新地址生成。

公开(公告)号：US09064546B2

公开(公告)日：2015-06-23

申请号：US14069188

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Young-Soo Sohn ,  Chul-Woo Park ,  Cheol-Heui Park

IPC: G11C8/10 ,  G11C8/06 ,  G11C7/12 ,  G11C29/18 ,  G11C16/24 ,  G11C29/12

CPC classification number: G11C8/06 ,  G11C7/12 ,  G11C8/10 ,  G11C16/24 ,  G11C29/18 ,  G11C2029/1204 ,  G11C2029/1806

Abstract: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.

Abstract translation: 可以提供一种存储器件，其包括包括多个子阵列的存储单元阵列，每个子阵列具有连接到位线的多个存储器单元; 配置为接收行地址和列地址的地址缓冲器; 以及列解码器，被配置为从地址缓冲器接收列地址，并且对于每个子阵列，基于应用的不同偏移值从多个列选择线中选择与列地址对应的列选择线 分别到子阵列。 所选择的列选择线分别对应于具有不同物理位置的位线，根据不同的偏移值。