公开(公告)号：US20240282828A1

公开(公告)日：2024-08-22

申请号：US18238872

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  KYOUNGWOO LEE ,  MINCHAN GWAK ,  Gukhee Kim ,  SANGCHEOL NA ,  Anthony Dongick Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An embodiment provides a semiconductor device including a semiconductor substrate having first and second surfaces opposite each other, a channel pattern disposed on the first surface of the semiconductor substrate; source/drain patterns disposed on the first surface of the semiconductor substrate and disposed at both sides of the channel pattern; first and second etch stop films disposed on the first surface of the semiconductor substrate; a contact electrode electrically connected to the source/drain patterns; a lower wire structure disposed on the second surface of the semiconductor substrate; and a through via that passes through the semiconductor substrate, the first etch stop film, and the second etch stop film to connect the contact electrode and the lower wire structure, wherein the through via includes a first portion contacting the contact electrode and a second portion contacting the first portion and disposed between the first portion and the lower wire structure.

公开(公告)号：US20240145556A1

公开(公告)日：2024-05-02

申请号：US18382616

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Hojun Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: An embodiment of the present inventive step provides a semiconductor device, comprising: first and second fin-type active patterns disposed on an upper surface of a substrate, and having different widths; first and second gate structures crossing the first and second fin-type active patterns, respectively; first and second source/drain regions disposed on the first and second fin-type active patterns, respectively; first and second contact structures connected to the first and second source/drain regions, respectively; a gate isolation structure adjacent to the first fin-type active pattern having a relatively large width; a buried conductive structure contacting one end surface of the gate isolation structure, and connected to the second contact structure; a conductive through-structure extending from a lower surface of the substrate, and connected to the buried conductive structure; and a first wiring layer electrically connected to the first contact structure and the buried conductive structure.

公开(公告)号：US20240128161A1

公开(公告)日：2024-04-18

申请号：US18379083

申请日：2023-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Sangcheol Na ,  Sora You ,  Kyoungwoo Lee ,  Minchan Gwak ,  Youngwoo Kim ,  Jinkyu Kim ,  Seungmin Cha

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is an integrated circuit device including a substrate, a plurality of semiconductor patterns on a first surface of the substrate, a gate electrode extending in a first direction and surrounding the semiconductor patterns, a source/drain region disposed on one side of the gate electrode, a vertical power wiring layer extending in a second direction, a liner structure including a first liner and a second liner, the first liner disposed on a lower portion of a sidewall of the vertical power wiring layer and including a first insulating material, and the second liner disposed on an upper portion of the sidewall of the vertical power wiring layer and including a second insulating material, a first contact disposed on the source/drain region and the vertical power wiring layer, and a back wiring structure disposed on a second surface of the substrate and electrically connected to the vertical power wiring layer.

公开(公告)号：US20240072117A1

公开(公告)日：2024-02-29

申请号：US18307259

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Jeewoong Kim ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Anthony Dongick Lee

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/823475 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.

公开(公告)号：US11744078B2

公开(公告)日：2023-08-29

申请号：US17085715

申请日：2020-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dawoon Jeong ,  Youngwoo Kim ,  Jaesung Kim ,  Hyoungryeol In

IPC: H10B43/50 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/50 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate in the first region and extending in different lengths along a second direction, perpendicular to the first direction in the second region, first separation regions penetrating the gate electrodes in the first and second regions, extending in the second direction, and spaced apart from each other in a third direction, perpendicular to the first and second directions, second separation regions penetrating the gate electrodes in the second region and spaced apart from each other in the second direction between the separation regions, and a first vertical structure penetrating the gate electrodes in the second region and closest to the first region, wherein a width of the second separation regions in the third direction is greater than a width of the first vertical structure, a first end point of the second separation regions adjacent to the first region is spaced apart from a central axis of the first dummy structure in the second direction, away from the first region.

公开(公告)号：US20210391346A1

公开(公告)日：2021-12-16

申请号：US17159727

申请日：2021-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Dawoon Jeong ,  Tak Lee ,  Jungmin Lee

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

公开(公告)号：US09601577B1

公开(公告)日：2017-03-21

申请号：US15251510

申请日：2016-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Youngwoo Kim ,  Jinhyun Shin ,  Jung Hoon Lee

IPC: H01L29/10 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  G11C16/08

CPC classification number: H01L27/11551 ,  H01L21/26506 ,  H01L21/28158 ,  H01L21/823462 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11246 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/1083 ,  H01L29/42368

Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.