公开(公告)号：US12027601B2

公开(公告)日：2024-07-02

申请号：US17815253

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/517 ,  H01L29/7831 ,  H01L29/78391

Abstract: A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.

公开(公告)号：US12014790B2

公开(公告)日：2024-06-18

申请号：US17815096

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Katherine H. Chiang ,  Chien-Hao Huang ,  Cheng-Yi Wu ,  Chung-Te Lin

IPC: G11C29/00 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/44 ,  G11C29/24 ,  G11C29/42 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

公开(公告)号：US20240172449A1

公开(公告)日：2024-05-23

申请号：US18422245

申请日：2024-01-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B41/23 ,  H10B41/27 ,  H10B41/35 ,  H10B43/23 ,  H10B51/20 ,  H10B51/40 ,  H10B51/50

CPC classification number: H10B51/30 ,  H10B41/23 ,  H10B41/27 ,  H10B41/35 ,  H10B43/23 ,  H10B51/20 ,  H10B51/40 ,  H10B51/50

Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

公开(公告)号：US20240145571A1

公开(公告)日：2024-05-02

申请号：US18150259

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Ting Lin ,  Yu-Ming Hsiang ,  Wei-Chih Wen ,  Yin-Hao Wu ,  Wu-Wei Tsai ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/0228 ,  H01L29/66969 ,  H01L29/78391 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

公开(公告)号：US20240063307A1

公开(公告)日：2024-02-22

申请号：US18500392

申请日：2023-11-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Neil Quinn Murray ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L29/7869 ,  H01L27/124 ,  H01L29/66969 ,  H01L27/127 ,  H01L27/1225 ,  H01L27/1255

Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.

公开(公告)号：US20240055517A1

公开(公告)日：2024-02-15

申请号：US17886472

申请日：2022-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chang Chiang ,  Yu-Chuan Shih ,  Chun-Chieh Lu ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/1159 ,  H01L29/516 ,  H01L29/6684

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

公开(公告)号：US20240023342A1

公开(公告)日：2024-01-18

申请号：US18363049

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B51/00

CPC classification number: H10B51/30 ,  H10B51/00 ,  H01L28/75 ,  H01L2924/1441

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

公开(公告)号：US20240006538A1

公开(公告)日：2024-01-04

申请号：US17857021

申请日：2022-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Po-Ting Lin ,  Kai-Wen Cheng ,  Sai-Hooi Yeong ,  Han-Ting Tsai ,  Ya-Ling Lee ,  Hai-Ching Chen ,  Chung-Te Lin ,  Yu-Ming Lin

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/1159

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L27/1159

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

公开(公告)号：US20230397426A1

公开(公告)日：2023-12-07

申请号：US17832673

申请日：2022-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Jiang ,  TsuChing Yang ,  Sheng-Chih Lai ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

公开(公告)号：US11832450B2

公开(公告)日：2023-11-28

申请号：US17867998

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

IPC: G11C11/22 ,  H10B51/30 ,  H01L27/12

CPC classification number: H10B51/30 ,  G11C11/223 ,  H01L27/1211

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.