公开(公告)号：US12002684B2

公开(公告)日：2024-06-04

申请号：US18057728

申请日：2022-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  B24B37/04 ,  B24B37/10 ,  C09G1/02

CPC classification number: H01L21/3212 ,  B24B37/044 ,  B24B37/107 ,  C09G1/02

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

公开(公告)号：US20220336367A1

公开(公告)日：2022-10-20

申请号：US17466425

申请日：2021-09-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hung Tsai ,  Chao-Hsun Wang ,  Pei-Hsuan Lee ,  Chih-Chien Chi ,  Ting-Kui Chang ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L23/532 ,  H01L29/417 ,  H01L21/768

Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.

公开(公告)号：US20190244804A1

公开(公告)日：2019-08-08

申请号：US16390691

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Ming Huang ,  Liang-Guang Chen ,  Ting-Kui Chang ,  Chun-Chieh Lin

IPC: H01L21/02 ,  H01L21/67 ,  B08B1/00 ,  B08B1/04 ,  H01L21/687 ,  B08B3/04 ,  H01L21/306

CPC classification number: H01L21/02043 ,  B08B1/002 ,  B08B1/04 ,  B08B3/04 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/30625 ,  H01L21/67028 ,  H01L21/67046 ,  H01L21/67092 ,  H01L21/687

Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

公开(公告)号：US11658065B2

公开(公告)日：2023-05-23

申请号：US16902203

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Chi-Hsiang Shen ,  Ting-Hsun Chang ,  Li-Chieh Wu ,  Hung Yen ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L21/768 ,  C09K3/14 ,  C09G1/02 ,  H01L21/321

CPC classification number: H01L21/7684 ,  C09G1/02 ,  C09K3/1463 ,  C09K3/1481 ,  H01L21/3212 ,  H01L21/76877

Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.

公开(公告)号：US11508585B2

公开(公告)日：2022-11-22

申请号：US16902180

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  C09G1/02 ,  B24B37/10 ,  B24B37/04

Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

公开(公告)号：US20220359263A1

公开(公告)日：2022-11-10

申请号：US17382873

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hsin Chan ,  Cai-Ling Wu ,  Chang-Wen Chen ,  Po-Hsiang Huang ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Jr-Hung Li ,  Jay Chiu ,  Ting-Kui Chang

IPC: H01L21/768 ,  H01L29/417

Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

公开(公告)号：US11322345B2

公开(公告)日：2022-05-03

申请号：US16390691

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Ming Huang ,  Liang-Guang Chen ,  Ting-Kui Chang ,  Chun-Chieh Lin

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/687 ,  H01L21/306 ,  B08B1/00 ,  B08B1/04 ,  B08B3/04

Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

公开(公告)号：US11211289B2

公开(公告)日：2021-12-28

申请号：US16556360

申请日：2019-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/3115 ,  H01L23/532

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US20190385909A1

公开(公告)日：2019-12-19

申请号：US16556360

申请日：2019-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.