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    MICROELECTRONIC DEVICE PACKAGE INCLUDING INDUCTOR AND SEMICONDUCTOR DEVICE
    11.
    发明公开
    MICROELECTRONIC DEVICE PACKAGE INCLUDING INDUCTOR AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240120297A1

    公开(公告)日：2024-04-11

    申请号：US17958254

    申请日：2022-09-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jie Chen ,  Rajen Maricon Murugan ,  Chittranjan Mohan Gupta ,  Yiqi Tang

    IPC: H01L23/66

    CPC classification number: H01L23/66 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6677

    Abstract: An apparatus includes: a first conductor layer patterned into parallel strips having a first end and an opposite second end formed on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers extending through the dielectric material; a second conductor layer in the multilayer package substrate spaced from the first conductor layer, the second conductor layer patterned into parallel strips having a first end and a second end, the second conductor layer coupled to the first conductor layer by vertical connectors formed of the conductive vertical connection layers at the first end and the second end, and a semiconductor die mounted to the device side surface of the multilayer package substrate that is spaced from and coupled to the second conductor.

    SEMICONDUCTOR DEVICE WITH A MULTILAYER PACKAGE SUBSTRATE
    14.
    发明申请
    SEMICONDUCTOR DEVICE WITH A MULTILAYER PACKAGE SUBSTRATE 有权

    公开(公告)号：US20230021179A1

    公开(公告)日：2023-01-19

    申请号：US17379549

    申请日：2021-07-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen

    IPC: H01L49/02 ,  H01F17/00 ,  H05K3/46 ,  H05K1/11 ,  H02M3/158

    Abstract: A semiconductor device includes a die having an input port and an output port. The semiconductor device also includes a multilayer package substrate with pads on a surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board. The multilayer package substrate also includes a passive filter comprising an input port and an output port, and a planar inductor. The planar inductor is coupled to a given pad of the pads of the multilayer package substrate with a first via of the multilayer package substrate and to the input port of the die with a second via of the multilayer package substrate. The planar inductor extends parallel to the surface of the multilayer package substrate.

    MULTI-CHANNEL GATE DRIVER PACKAGE WITH GROUNDED SHIELD METAL
    17.
    发明公开
    MULTI-CHANNEL GATE DRIVER PACKAGE WITH GROUNDED SHIELD METAL 审中-公开

    公开(公告)号：US20230215811A1

    公开(公告)日：2023-07-06

    申请号：US17569724

    申请日：2022-01-06

    Applicant: Texas Instruments Incorporated

    Inventor： Yiqi Tang ,  Rajen Murugan ,  Jie Chen

    IPC: H01L23/552 ,  H03K17/042 ,  H01L23/495 ,  H01L25/00

    CPC classification number: H01L23/552 ,  H03K17/04206 ,  H01L23/49503 ,  H01L25/50 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48

    Abstract: A multi-channel gate driver package includes a leadframe including a first, second, and third die pad. A transmitter die includes first and second transmitter signal bond pads, a first receiver die including a second signal bond pad, and a second receiver die including a third signal bond pad. A bond wire is between the first transmitter signal bond pad and the second signal bond pad, and between the second transmitter signal bond pad and third signal bond pad. A ring shield is around the respective signal bond pads. A downbond is from the second ring shield to the second die pad, and from the third ring shield to the third die pad. A connection connects the first and second transmitter ring shield to at least one ground pin of the package. The second and third die pad each include a direct integral connection to the ground pin.

    SEMICONDUCTOR PACKAGE WITH SHUNT AND PATTERNED METAL TRACE
    18.
    发明申请
    SEMICONDUCTOR PACKAGE WITH SHUNT AND PATTERNED METAL TRACE 有权

    公开(公告)号：US20220384353A1

    公开(公告)日：2022-12-01

    申请号：US17500086

    申请日：2021-10-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

    IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

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