公开(公告)号：US12243809B2

公开(公告)日：2025-03-04

申请号：US18306808

申请日：2023-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/07

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

公开(公告)号：US11908780B2

公开(公告)日：2024-02-20

申请号：US17518554

申请日：2021-11-03

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Lance Cole Wright ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/074 ,  H01L25/16 ,  H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40145 ,  H01L2224/40177 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83815 ,  H01L2224/84815 ,  H01L2224/92246 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/2064

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

公开(公告)号：US20230268253A1

公开(公告)日：2023-08-24

申请号：US18306808

申请日：2023-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L25/074 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/3121 ,  H01L23/49586 ,  H01L23/49562 ,  H01L21/4828 ,  H01L24/27 ,  H01L24/83 ,  H01L25/50 ,  H01L21/565 ,  H01L24/32 ,  H01L24/29 ,  H01L23/49548 ,  H01L2924/13091 ,  H01L2224/83815 ,  H01L2224/83192 ,  H01L2224/32245 ,  H01L2224/2919 ,  H01L2224/2731 ,  H01L2924/0665

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

公开(公告)号：US20220208692A1

公开(公告)日：2022-06-30

申请号：US17138981

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Osvaldo Jorge Lopez ,  Lance Cole Wright

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.

公开(公告)号：US11024564B2

公开(公告)日：2021-06-01

申请号：US16445836

申请日：2019-06-19

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

公开(公告)号：US10062624B2

公开(公告)日：2018-08-28

申请号：US15634472

申请日：2017-06-27

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L23/13 ,  H01L23/373 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/3738 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/3303 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/00014

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

公开(公告)号：US09553068B2

公开(公告)日：2017-01-24

申请号：US14725377

申请日：2015-05-29

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Juan Herbsommer

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/28 ,  H01L23/498

CPC classification number: H01L24/49 ,  H01L23/28 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49883 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05078 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/29026 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/00015

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract translation: 集成电路（“IC”）组件包括其顶表面上具有金属化层的IC管芯。 多个引线在其第一端部处接合到金属化层。 导电层附接到金属化层并覆盖引线的第一端。

公开(公告)号：US20160133534A1

公开(公告)日：2016-05-12

申请号：US14534254

申请日：2014-11-06

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/3738 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/15153 ,  H01L2924/157

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

Abstract translation: 封装晶体管器件（100）包括半导体芯片（101），其包括具有分布在第一和相对的第二芯片侧上的端子的晶体管; 以及构成为脊（111）的低等级硅（lg-Si）的板坯（110），其构成包括适于容纳所述芯片的凹陷中心区域的凹陷，所述脊具有在第一平面中的第一表面和所述凹入 中心区域在第二平面中具有与第一平面间隔开至少等于芯片厚度的深度（112）的第二表面，所述脊被设备端子（120; 121）覆盖，所述深度连接到具有 连接第一芯片侧的端子，使得相对的第二芯片侧的端子（103）与板条脊上的装置端子共面。

公开(公告)号：US20150318233A1

公开(公告)日：2015-11-05

申请号：US14800903

申请日：2015-07-16

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/07 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49575 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H02M3/155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/05599

Abstract: A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Abstract translation: 电源系统具有带引线和焊盘的QFN引线框架。 面对电路板的焊盘表面具有凹陷的部分，其深度和轮廓适合于并置并联和控制FET半导体芯片。 控制FET的输入端子和同步FET的接地输出端子与焊盘（开关节点端子）的未凹入部分共面，使得所有端子可以直接附接到电路板的触点。 驱动器和控制芯片垂直地堆叠到相对的焊盘表面并且封装在封装复合体中。

公开(公告)号：US20150262965A1

公开(公告)日：2015-09-17

申请号：US14725377

申请日：2015-05-29

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Juan Herbsommer

IPC: H01L23/00 ,  H01L23/28 ,  H01L23/498

CPC classification number: H01L24/49 ,  H01L23/28 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49883 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05078 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/29026 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/00015

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract translation: 集成电路（“IC”）组件包括其顶表面上具有金属化层的IC管芯。 多个引线在其第一端部处接合到金属化层。 导电层附接到金属化层并覆盖引线的第一端。