公开(公告)号：US09653577B2

公开(公告)日：2017-05-16

申请号：US15220910

申请日：2016-07-27

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Scott G. Balster

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L21/266

CPC classification number: H01L27/0922 ,  H01L21/266 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

公开(公告)号：US20170125528A1

公开(公告)日：2017-05-04

申请号：US15403748

申请日：2017-01-11

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L29/41 ,  H01L21/324 ,  H01L21/225 ,  H01L21/3215 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

公开(公告)号：US20160315141A1

公开(公告)日：2016-10-27

申请号：US15175192

申请日：2016-06-07

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  Binghua Hu ,  Henry Litzmann Edwards

IPC: H01L29/06 ,  H01L21/266 ,  H01L21/02 ,  H01L21/74 ,  H01L29/167 ,  H01L21/265 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/0623 ,  H01L21/02164 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/324 ,  H01L21/74 ,  H01L29/0646 ,  H01L29/167 ,  H01L29/456

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

Abstract translation: 半导体器件具有通过以高剂量和低能量将锑和/或砷注入p型第一外延层而形成的n型掩埋层，并且以低剂量和高能量注入磷。 热驱动过程扩散并激活重掺杂物和磷。 锑和砷不会显着扩散，保持埋层主层的狭窄轮廓。 磷扩散以提供在主层下面几微米厚的轻掺杂层。 在掩埋层上生长外延p型层。

公开(公告)号：US09337106B2

公开(公告)日：2016-05-10

申请号：US14575457

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  Binghua Hu

IPC: H01L21/425 ,  H01L21/70 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L21/0274 ,  H01L21/02694 ,  H01L21/0271 ,  H01L21/266 ,  H01L21/32 ,  H01L21/426 ,  H01L21/823493 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.

Abstract translation: 一种使用一个光致抗蚀剂图案和注入工艺步骤在晶片的表面处形成至少两种不同掺杂水平的工艺。 开发抗蚀剂层（但不烘烤）以形成第一抗蚀剂几何形状和多个亚光刻抗蚀剂几何形状。 烘烤抗蚀剂层，使得亚光刻抗蚀剂几何形状回流到具有小于第一抗蚀剂几何形状的厚度的连续的第二抗蚀剂几何形状。 高能量注入通过第二抗蚀剂几何体注入掺杂剂，但不通过第一抗蚀剂几何形状。 低能量植入物被第一和第二抗蚀剂几何形状阻挡。

公开(公告)号：US09865691B2

公开(公告)日：2018-01-09

申请号：US15403748

申请日：2017-01-11

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L21/8242 ,  H01L29/41 ,  H01L29/45 ,  H01L21/02 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/324

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

公开(公告)号：US09843322B2

公开(公告)日：2017-12-12

申请号：US15067928

申请日：2016-03-11

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03L5/00 ,  H03K17/687 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09673273B2

公开(公告)日：2017-06-06

申请号：US15175192

申请日：2016-06-07

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  Binghua Hu ,  Henry Litzmann Edwards

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/167 ,  H01L21/74

CPC classification number: H01L29/0623 ,  H01L21/02164 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/324 ,  H01L21/74 ,  H01L29/0646 ,  H01L29/167 ,  H01L29/456

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

公开(公告)号：US09431480B1

公开(公告)日：2016-08-30

申请号：US14671572

申请日：2015-03-27

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Scott G. Balster

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/266 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

Abstract translation: 多指横向高压晶体管（MFLHVT）包括掺杂有第一掺杂剂类型的衬底，掺杂第二掺杂剂的衬底以及掺杂有第一类型的具有稀释BDL部分（DBDL）的掩埋漂移层（BDL），其包括稀释条纹 。 掺杂第二类型的半导体表面在BDL上。 电介质隔离区域具有限定第一间隙区域（第一MOAT）中的第一有源区域和第二间隙区域（第二MOAT）中的第二有源区域的间隙。 漏极包括第二MOAT中的漏极指与第一MOAT中的源极指与每个掺杂的第二类型相互指向。 DBDL位于指尖漂移区域内，与第一和第二MOAT之间的排水指尖和/或来源指尖相关联。 栅极堆叠在源极和漏极之间的半导体表面上。 稀释条纹具有在其各自位置处以漂移长度单调增加的条带宽度。

公开(公告)号：US09245998B2

公开(公告)日：2016-01-26

申请号：US14578710

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L29/78 ,  H01L29/76 ,  H01L21/336 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

Abstract translation: 一种具有多个电流通道的LDMOS晶体管的集成电路和方法。 第一电流通道在掩埋的p型扩散之上，并且第二个电流通道在掩埋的p型扩散之下。

公开(公告)号：US11482613B2

公开(公告)日：2022-10-25

申请号：US16272025

申请日：2019-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer P. Pendharkar ,  John Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.