公开(公告)号：US5918073A

公开(公告)日：1999-06-29

申请号：US884432

申请日：1997-06-27

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F3/06 ,  G06F3/16 ,  G06F5/10 ,  G06F3/00

CPC分类号： G06F5/10 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0674 ,  G06F3/16

摘要： A system and method are presented for equalizing data buffer storage and fetch rates of peripheral devices. A computer system of the present invention includes a central processing unit (CPU), first and second peripheral devices, and a data buffer. The first peripheral device stores data within the data buffer, and the second peripheral device fetches data from the data buffer. A fraction of the data buffer contains unread data (i.e. data stored within the data buffer by the first peripheral device and not yet fetched by the second peripheral device). The first peripheral device includes a reload register, the contents of which determines the rate at which the first peripheral device stores data within the data buffer. The CPU produces a reload value, which is stored within the reload register, such that the rate at which the first peripheral device stores the data within the data buffer is made substantially equal to the rate at which the second peripheral device fetches the data from the data buffer. The data buffer is preferably operated a first-in-first-out manner, and includes a write pointer and a read pointer. The CPU preferably produces the reload value such that approximately half the memory locations within the data buffer contain unread data at any given time.

摘要翻译： 提出了一种系统和方法，用于平衡外围设备的数据缓冲存储和提取速率。 本发明的计算机系统包括中央处理单元（CPU），第一和第二外围设备以及数据缓冲器。 第一外围设备将数据存储在数据缓冲器内，第二外围设备从数据缓冲器中取出数据。 数据缓冲器的一小部分包含未读数据（即由第一外围设备存储在数据缓冲器内并且尚未被第二外围设备取出的数据）。 第一外围设备包括重新加载寄存器，其内容确定第一外围设备在数据缓冲器内存储数据的速率。 CPU产生存储在重新加载寄存器内的重载值，使得第一外围设备将数据存储在数据缓冲器内的速率基本上等于第二外围设备从数据缓冲器中提取数据的速率 数据缓冲区。 数据缓冲器优选地以先进先出的方式操作，并且包括写指针和读指针。 CPU优选地产生重载值，使得数据缓冲器内的大约一半存储器位置在任何给定时间包含未读数据。

公开(公告)号：US5898886A

公开(公告)日：1999-04-27

申请号：US752647

申请日：1996-11-19

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F13/42

CPC分类号： G06F13/423

摘要： A computer system is presented having various peripheral devices coupled to a PCI local bus (i.e., an expansion bus), a subset of the peripheral devices having quaternary interfaces configured to communicate via quaternary signals conveyed upon the PCI local bus. The various peripheral devices may include a video/graphics card, a sound card, a hard disk drive, a CD-ROM drive, and a network interface card. When data is transferred from a master device to a target device, and the master and target devices both have quaternary interfaces, the master device converts the data to quaternary signals before transmitting the data the target device via the PCI local bus. The target device receives the quaternary signals from the PCI local bus and converts the quaternary signals to the binary data. Two binary digits (i.e., bits) of information are advantageously conveyed using quaternary signals in the time required to transmit a single bit using binary signals, thus providing increased efficiency and reduced bus bandwidth requirements. If either device does not include a quaternary interface, the data is transferred using conventional binary signals. A handshaking protocol may be used to determine if both the master and target devices include a quaternary interface. The handshaking protocol is implemented using handshaking signals conveyed over additional control lines added to the PCI local bus. Alternatively, a configuration memory may be included in the quaternary interface of the master device to reduce the required number of additional control lines from two to one.

摘要翻译： 呈现具有耦合到PCI本地总线（即，扩展总线）的各种外围设备的计算机系统，具有被配置为经由PCI本地总线上传送的四进制信号进行通信的四进制接口的外围设备的子集。 各种外围设备可以包括视频/图形卡，声卡，硬盘驱动器，CD-ROM驱动器和网络接口卡。 当数据从主设备传输到目标设备，并且主设备和目标设备都具有四元接口时，主设备在通过PCI本地总线传送目标设备的数据之前将数据转换为四进制信号。 目标设备从PCI本地总线接收四进制信号，并将四进制信号转换为二进制数据。 在使用二进制信号发送单个位所需的时间内，使用四进制信号有利地传送信息的两个二进制数字（即比特），从而提供更高的效率和降低的总线带宽要求。 如果任何一个设备不包括四元接口，则使用常规二进制信号传输数据。 握手协议可用于确定主设备和目标设备是否包括四元接口。 使用通过添加到PCI本地总线的附加控制线传送的握手信号实现握手协议。 或者，可以在主设备的四元接口中包括配置存储器，以将所需数量的附加控制线从两个减少到一个。

公开(公告)号：US5859995A

公开(公告)日：1999-01-12

申请号：US373689

申请日：1995-01-17

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： H03K19/003 ,  G06F3/16 ,  G06F7/02 ,  G06F9/38 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  G10H7/02 ,  H03K3/02 ,  H03K23/68 ,  H03M3/02 ,  H03M7/32 ,  G06F1/04

CPC分类号： G06F3/16 ,  G06F7/026 ,  G06F9/3869 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H7/02 ,  H03K23/68 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

摘要： A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the upstream SM output state and selected data at the triggering circuit input. The triggering circuit and the upstream SM are clocked from a common signal preventing the upstream SM from changing state before the triggering circuit produces the proper signal to impose the expected state on the downstream SM. The downstream SM takes on the correct output state in dependable correspondence with a selected upstream SM output state. In a preferred embodiment, a D flip-flop generates a triggering signal in response to a selected combination of upstream SM output state and system data. The D flip-flop triggering signal imposes a selected output state on a downstream SM through the asynchronous SET and CLEAR inputs of the downstream SM flip-flops. Because the D flip-flop and upstream SM are both clocked off the same trailing edge of the WRITE line, the upstream SM and D flip-flop change state together, preventing the upstream SM from changing state before the triggering signal is generated.

摘要翻译： 触发电路消除上游和下游状态机（“SM”）的差分组合逻辑时钟的传播差异。 触发电路响应于在触发电路输入处出现上游SM输出状态和所选择的数据的适当组合，在下游SM上施加输出状态。 触发电路和上游SM从公共信号计时，防止上游SM在触发电路产生适当信号之前改变状态，以将预期状态施加在下游SM上。 下游SM与选择的上游SM输出状态可靠地对应地进行正确的输出状态。 在优选实施例中，D触发器响应于所选择的上游SM输出状态和系统数据的组合而产生触发信号。 D触发器触发信号通过下游SM触发器的异步SET和CLEAR输入在下游SM上施加选择的输出状态。 因为D触发器和上游SM都被写入WRITE线的相同后沿，所以上行SM和D触发器一起改变状态，从而防止上游SM在产生触发信号之前改变状态。

公开(公告)号：US07607031B2

公开(公告)日：2009-10-20

申请号：US11482269

申请日：2006-07-07

申请人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

发明人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

摘要翻译： 计算机系统包括通过通信链路耦合的第一和第二集成电路。 通信链路以省电模式运行，其中数据不通过链路发送。 周期性地，通信链路进入训练阶段，其中通过通信链路在预定时间段内传送训练模式。 在预定时间段过去之后，通信链路返回到省电模式。 与通信链路分离并且耦合在第一和第二集成电路之间的至少一个边带信号用于指示何时从功率节省模式进入训练阶段并退出训练阶段并返回到省电模式。

公开(公告)号：US07421525B2

公开(公告)日：2008-09-02

申请号：US10842296

申请日：2004-05-10

申请人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

发明人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00 ,  G11C5/06

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控​​制集线器。 存储器模块通过多个存储器链路串联地连接到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

公开(公告)号：US07308514B1

公开(公告)日：2007-12-11

申请号：US10647397

申请日：2003-08-25

申请人： Larry D. Hewitt ,  Dale E. Gulick

发明人： Larry D. Hewitt ,  Dale E. Gulick

IPC分类号： G06F13/38

CPC分类号： G06F13/4027

摘要： Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

摘要翻译： 计算机系统配置资源包括在第一和第二集成电路中的第一和第二控制电路。 通过多个逻辑管道传送数据的通信链路连接两个集成电路。 链路的配置使用包括第一控制电路内的上游（位于最靠近CPU）的配置寄存器和第二控制电路（（位于距离CPU最远）配置寄存器）的链路桥接器，链路头 包括用于第一控制电路的上行数据和第二控制电路的下行数据用于初始化链路，上游和下行数据可以包括指定通信链路大小的信息。

公开(公告)号：US06928528B1

公开(公告)日：2005-08-09

申请号：US10266118

申请日：2002-10-07

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F12/06 ,  G06F13/40 ,  H04L7/02 ,  H04L12/46

CPC分类号： H04L12/4625 ,  G06F13/4059 ,  H04L7/005 ,  H04L7/02

摘要： A method and apparatus for guaranteed data synchronization. In one embodiment, a data synchronization unit includes a memory unit, a write pointer unit, a read pointer unit, and synchronization pulse logic. The memory unit may receive information from a source external to the data synchronization unit. The write pointer may specify an address within the memory where incoming information is to be written. A read pointer outgoing information is to be read from. The data synchronization unit may also include synchronization pulse logic. The synchronization pulse logic may be configured to, in a synchronization mode, to generate a synchronization pulse. In response to an assertion of the synchronization pulse, the read pointer may be initialized such that data read out of the memory unit is valid (i.e. guaranteed to meet electrical requirements) at that time.

摘要翻译： 一种用于保证数据同步的方法和装置。 在一个实施例中，数据同步单元包括存储器单元，写指针单元，读指针单元和同步脉冲逻辑。 存储器单元可以从数据同步单元外部的源接收信息。 写指针可以指定存储器内的地址，其中输入信息将被写入。 读取指针传出信息将被读取。 数据同步单元还可以包括同步脉冲逻辑。 同步脉冲逻辑可以被配置为在同步模式下产生同步脉冲。 响应于同步脉冲的断言，可以对读指针进行初始化，使得从存储器单元读出的数据在此时有效（即保证满足电气要求）。

公开(公告)号：US06557048B1

公开(公告)日：2003-04-29

申请号：US09431364

申请日：1999-11-01

申请人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

发明人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/4059

摘要： A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge. The I/O node may, for example, produce and/or provide a first transaction followed by a second transaction. The host bridge may dispatch the second transaction with respect to the first transaction according to a predetermined set of ordering rules. For example, the host bridge may: (i) receive the first and second transactions, (ii) dispatch the first transaction within the processing subsystem, and (iii) dispatch the second transaction within the processing subsystem dependent upon progress of the first transaction within the processing subsystem and the predetermined set of ordering rules.

摘要翻译： 提出了一种实现用于排序输入/输出（I / O）存储器操作的系统和方法的计算机系统。 在一个实施例中，计算机系统包括处理子系统和I / O子系统。 处理子系统包括通过相干通信链路互连的多个处理节点。 每个处理节点可以包括执行软件指令的处理器。 I / O子系统包括通过非相干通信链路串联耦合的一个或多个I / O节点。 每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 其中一个处理节点包括一个主机桥，它转换在处理子系统和I / O子系统之间移动的数据包。 其中一个I / O节点耦合到包括主机桥的处理节点。 耦合到处理节点的I / O节点产生和/或提供具有处理子系统内包含主机桥的处理节点的目的地或目标的事务。 I / O节点可以例如产生和/或提供第一事务，随后是第二事务。 主桥可以根据预定的一组排序规则来分派关于第一事务的第二事务。 例如，主桥可以：（i）接收第一和第二事务，（ii）在处理子系统内调度第一事务，以及（iii）根据第一事务的进度在处理子系统内调度第二事务 处理子系统和预定的一套排序规则。

公开(公告)号：US6167492A

公开(公告)日：2000-12-26

申请号：US220487

申请日：1998-12-23

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F13/16 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

公开(公告)号：US5956493A

公开(公告)日：1999-09-21

申请号：US612535

申请日：1996-03-08

申请人： Larry D. Hewitt ,  Scott E. Swanstrom

发明人： Larry D. Hewitt ,  Scott E. Swanstrom

IPC分类号： G06F13/364 ,  G06F13/36 ,  G06F13/362

CPC分类号： G06F13/364

摘要： A computer system is provided for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "request latency" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral requested ownership of the bus. An arbitration control unit is coupled to the request latency counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the latency signal corresponding to the device. Accordingly, as the time from when a peripheral device requests the bus increases, the level of arbitration priority given to that peripheral also increases. A set of programmable registers are provided to allow software programming of the initial count value associated with each request latency counter. The request latency counter for a particular device may further be held or inhibited from counting to provide a constant level of priority for that particular peripheral device.

摘要翻译： 提供了一种用于控制总线的所有权的计算机系统，多个实时资源和非实时资源耦合到总线。 总线仲裁器包括用于检测多个总线主机的总线请求信号的请求检测单元，以及用于产生相应的授权信号的授权发生器，用于指示总线的所有权授权。 还提供了称为“请求延迟”计数器的一组计数器，其中单独的计数器单元对应于每个总线主机。 每个计数器被配置为产生指示从外围设备请求所有总线的时间起经过的时间的信号。 仲裁控制单元耦合到请求等待时间计数器，请求检测单元和用于处理输入总线请求信号的授权发生器。 仲裁控制单元被配置为基于与设备相对应的等待时间信号来动态地改变给予每个外围设备的仲裁优先级。 因此，随着外围设备请求总线的时间增加，给予该外设的仲裁优先级也增加。 提供一组可编程寄存器以允许与每个请求延迟计数器相关联的初始计数值的软件编程。 特定设备的请求等待时间计数器可进一步被保持或禁止计数，以为该特定外围设备提供恒定的优先级。