公开(公告)号：US09543511B2

公开(公告)日：2017-01-10

申请号：US14645878

申请日：2015-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting Sung ,  Chang-Ming Wu ,  Hsia-Wei Chen ,  Shih-Chang Liu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

Abstract translation: 本公开涉及具有RRAM单元的集成电路器件和相关联的形成方法。 在一些实施例中，集成电路器件具有由下部ILD层围绕的下部金属互连层和设置在下部金属互连层上的底部电极。 底部电极具有被底部电介质层包围的下部和比下部更宽的上部。 底部介电层设置在下部金属互连层和下部ILD层之上。 集成电路器件还具有位于底部电极上的可变电阻的RRAM电介质，以及位于RRAM电介质上方的顶部电极。 集成电路器件还具有位于底部电介质层上方的顶部电介质层，该电介质层邻接底部电极的上部，RRAM电介质和顶部电极的侧壁。

公开(公告)号：US20160336415A1

公开(公告)日：2016-11-17

申请号：US14713462

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/788

Abstract: A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided.

Abstract translation: 提供了一种用于提高擦除速度的分离式闪存单元。 擦除栅极和浮栅在半导体衬底上横向隔开。 浮动栅极具有朝向擦除栅极增加的高度，与擦除栅极相邻的凹面侧表面，并且尖端限定了凹面侧壁表面与浮动栅极的上表面的界面。 控制栅极和侧壁间隔物布置在浮动栅极的上表面上。 控制门横向偏离浮动栅极的顶端，并且侧壁间隔件横向设置在控制栅极和尖端之间。 还提供了一种用于制造分裂栅极闪存单元的方法。

公开(公告)号：US20160307909A1

公开(公告)日：2016-10-20

申请号：US14688201

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/30625 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344

Abstract: The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.

Abstract translation: 本公开涉及一种集成电路（IC），其包括闪存器件区域，其包括布置在半导体衬底上的一对分裂栅极闪存单元。 一对分裂栅极闪存单元分别具有包括多晶硅栅极和上覆硅化物层的控制栅极（CG）。 包括一个或多个高k金属栅极（HKMG）晶体管的外围电路在横向偏离闪存器件区域的位置上布置在半导体衬底的上方。 一个或多个HKMG晶体管具有金属栅电极，其上表面低于硅化物层的上表面。 还提供了一种制造IC的方法。

公开(公告)号：US09391151B2

公开(公告)日：2016-07-12

申请号：US14493538

申请日：2014-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Tsung-Hsueh Yang ,  Sheng-Chieh Chen ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.

Abstract translation: 一些实施例涉及具有不对称浮动门几何形状的存储器件。 控制门布置在浮动门上。 擦除栅极横向布置在浮动栅极附近，并且通过隧道电介质层与浮动栅极分离。 侧壁间隔件沿着控制栅极的垂直侧壁并且在浮动栅极的上表面上方布置。 浮动门上表面的一部分形成水平延伸通过侧壁间隔物的“凸缘”或尖角。 浮动栅极的侧壁形成凹入表面，其从凸缘向下朝向浮动门内的颈部区域逐渐变细。 与具有平面侧壁表面的浮动栅极相比，该凸缘提供了更快的隧道隧道隧穿隧道介电层的路径。 因此，该凸起因此提高了存储器件的擦除速度。

公开(公告)号：US09391085B2

公开(公告)日：2016-07-12

申请号：US14454872

申请日：2014-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/66 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L27/11568 ,  H01L21/0217 ,  H01L21/28282 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792

Abstract: Some embodiments of the present disclosure relate to a split gate memory cell which includes a select gate and a memory gate. The select gate has a planar upper surface disposed over a semiconductor substrate and is separated from the substrate by a gate dielectric layer. The memory gate has a planar upper surface arranged at one side of the select gate and is separated from the substrate by a charge trapping layer. The charge trapping layer extends under the memory gate. A first spacer is disposed above the memory gate and is separated from the memory gate by a first dielectric liner. The first dielectric liner extends upwardly along an upper sidewall of the charge trapping layer; and source/drain regions are disposed in the semiconductor substrate at opposite sides of the select gate and the memory gate.

Abstract translation: 本公开的一些实施例涉及包括选择栅极和存储器栅极的分离栅极存储器单元。 选择栅极具有设置在半导体衬底上的平面上表面，并且通过栅极介电层与衬底分离。 存储器栅极具有布置在选择栅极的一侧的平面上表面，并且通过电荷捕获层与衬底分离。 电荷捕获层在存储栅下方延伸。 第一间隔件设置在存储器栅极上方并且通过第一电介质衬垫与存储器栅极分离。 第一电介质衬垫沿电荷俘获层的上侧壁向上延伸; 并且源极/漏极区域在选择栅极和存储栅极的相对侧设置在半导体衬底中。

公开(公告)号：US20160111510A1

公开(公告)日：2016-04-21

申请号：US14980165

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed laterally adjacent to the select gate and on a first side of the select gate. A charge trapping layer is formed lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate. A memory gate is formed over the charge trapping layer and on the second side of the select gate. The sacrificial spacer is removed. The resulting semiconductor structure is also provided.

Abstract translation: 提供了一种制造分离栅闪存单元的方法。 选择栅极形成在半导体衬底上。 牺牲隔离物横向邻近选择栅极并在选择栅极的第一侧上形成。 在选择栅极和牺牲隔离物的上表面上形成电荷捕获层，并且进一步在选择栅极的与选择栅极的第一侧相对的第二侧上衬里选择栅极的侧壁表面。 存储栅极形成在电荷俘获层上和选择栅极的第二侧上。 去除牺牲隔离物。 还提供所得的半导体结构。

公开(公告)号：US20160064401A1

公开(公告)日：2016-03-03

申请号：US14468410

申请日：2014-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract translation: 提供了具有非对称轮廓的硬掩模的分裂栅极闪存单元器件的半导体结构。 半导体结构的半导体衬底包括第一源极/漏极区域和第二源极/漏极区域。 半导体结构的控制栅极和存储栅极在第一和第二源/漏区之间的半导体衬底上间隔开。 半导体结构的电荷捕获电介质结构被布置在存储器栅极的相邻侧壁和控制栅极之间，并且布置在存储器栅极下方。 半导体结构的硬掩模布置在控制栅极上并且包括不对称轮廓。 不对称轮廓在远离记忆门的高度逐渐变细。 还提供了一种用于制造具有不对称轮廓的硬掩模的一对分裂栅极闪存单元器件的方法。

公开(公告)号：US20150263010A1

公开(公告)日：2015-09-17

申请号：US14210796

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L27/11 ,  H01L27/115

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

Abstract translation: 本公开涉及一种在采用替代门技术的HKMG集成电路中嵌入ESF3存储器的方法。 ESF3存储器形成在凹陷的衬底上，防止在ILD层执行的CMP工艺期间对存储器控制栅极的损坏。 在存储单元和外围电路边界之间的过渡区域中也形成非对称隔离区。

公开(公告)号：US20150236110A1

公开(公告)日：2015-08-20

申请号：US14276631

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/42348 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer. A first etch back process is formed on the first layer of conductive material to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer. A conformal silicide-blocking layer is then formed which extends over the etched back first layer of conductive material and over the top surface of the sacrificial spacer.

Abstract translation: 在形成分离栅极存储单元的方法中，在半导体衬底上形成牺牲间隔物。 在牺牲间隔物的顶表面和侧壁上形成第一导电材料层。 在第一导电材料层上形成第一回蚀工艺以暴露牺牲间隔物的顶表面和牺牲间隔物的上侧壁区域。 然后形成保形硅化物阻挡层，其在蚀刻后的第一导电材料层上方并在牺牲隔离物的顶表面上方延伸。

公开(公告)号：US20190241430A1

公开(公告)日：2019-08-08

申请号：US16384066

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

IPC: B81C1/00 ,  H01L23/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2207/07 ,  B81C1/00333 ,  B81C2201/0132 ,  B81C2203/0109 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/091 ,  H01L2224/80013 ,  H01L2224/80895

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.