公开(公告)号：US09559021B2

公开(公告)日：2017-01-31

申请号：US15060807

申请日：2016-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/306 ,  B24B9/06 ,  B24B7/22 ,  B24B21/00

CPC classification number: H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.

Abstract translation: 晶片抛光工艺包括抛光晶片背面的中心区域，抛光晶片背面的周边区域，抛光中心区域，以及抛光周边区域。 该过程可以显着减少划痕相关的晶片断裂，可以校正晶片上的焦点，并可以替代使用化学蚀刻剂的清洗工艺。 抛光和抛光可以包括抛光和抛光斜面区域。 进一步的改进包括用具有柔软背衬的研磨垫，抛光或抛光，具有相对较软的磨料颗粒的垫，抛光或抛光，其中由磨料颗粒制成的研磨垫已被分选并选择成规则形状，冲洗正被抛光的表面 用包含减摩剂的水溶液抛光，并用具有20k或更细砂粒或非研磨垫的研磨垫进行抛光。

公开(公告)号：US20200027760A1

公开(公告)日：2020-01-23

申请号：US16587788

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin ,  Hsin-Hsien Lu

IPC: H01L21/67 ,  H01L21/02 ,  B24B37/34

Abstract: The present disclosure, in some embodiments, relates to a brush cleaning apparatus. The brush cleaning apparatus includes a wafer support configured to support a wafer. The brush cleaning apparatus also includes a cleaning brush including a porous material coupled to a core material. An uppermost surface of the porous material defines a planar cleaning surface. A first nozzle is configured to apply a first cleaning liquid directly between the wafer and the planar cleaning surface of the cleaning brush.

公开(公告)号：US20190270180A1

公开(公告)日：2019-09-05

申请号：US16419256

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin

IPC: B24B53/017 ,  H01L21/67 ,  H01L21/306 ,  B24B37/10 ,  B24B37/30 ,  B24B37/32 ,  B24B53/02

Abstract: The present disclosure, in some embodiments, relates to a polishing system. The polishing system includes a carrier head configured to enclose a wafer. The carrier head has a retainer ring configured to laterally surround the wafer and an abrasive structure that partially covers a lower surface of the retainer ring. A membrane support is surrounded by the retainer ring and defines one or more ports. One or more chambers are coupled to the one or more ports and are defined by the membrane support and a flexible membrane having a lower surface configured to contact the wafer.

公开(公告)号：US20180358243A1

公开(公告)日：2018-12-13

申请号：US16108464

申请日：2018-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin ,  Hsin-Hsien Lu

IPC: H01L21/67 ,  B24B37/34 ,  H01L21/02

Abstract: A method of processing a wafer is disclosed. The method includes, in some embodiments, causing a relative movement between a cleaning brush and a wafer. During the relative movement, a planar cleaning surface of the cleaning brush is brought into contact with a surface of the wafer to remove contaminants from the surface of the wafer. A first size of the cleaning brush, in a plan view, is larger than a second size of the wafer in the plan view.

公开(公告)号：US20170157742A1

公开(公告)日：2017-06-08

申请号：US15436953

申请日：2017-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin

IPC: B24B53/017 ,  H01L21/67 ,  H01L21/306 ,  B24B37/10 ,  B24B37/32

CPC classification number: B24B53/017 ,  B24B37/10 ,  B24B37/32 ,  B24B53/02 ,  H01L21/30625 ,  H01L21/67253

Abstract: In some embodiments, the present disclosure relates to a method of performing a planarization process. The method may be performed by placing a wafer between a carrier head and an upper surface of a polishing pad. The carrier head has a retainer ring configured to surround the wafer, and the retainer ring has an abrasive structure configured to contact the upper surface of the polishing pad. Pressures within one or more chambers surrounded by the carrier head are independently regulated. The one or more chambers have one or more interior surfaces having a flexible membrane. The flexible membrane has a lower surface configured to contact the wafer. At least one of the carrier head or the polishing pad are moved relative to the other, and a roughness of the upper surface of the polishing pad is maintained within a predetermined range by using the abrasive structure of the retainer ring.

公开(公告)号：US20170125237A1

公开(公告)日：2017-05-04

申请号：US15407893

申请日：2017-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC: H01L21/02 ,  B24B9/06 ,  B24B7/22 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

Abstract: Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.

公开(公告)号：US09478431B2

公开(公告)日：2016-10-25

申请号：US14967741

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L21/31055 ,  H01L21/02282 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0692 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC.

Abstract translation: 本公开提供了在一些实施例中制造集成电路器件的方法。 在该方法中，通过一系列操作来处理半导体衬底，以在半导体衬底上形成拓扑可变表面。 地形可变表面在半导体衬底上的高度变化。 在地形可变表面上提供聚合物底部抗反射涂层（BARC）。 执行化学机械抛光以去除BARC的第一部分，并且蚀刻实现BARC的自上而下的凹陷。

公开(公告)号：US20160190023A1

公开(公告)日：2016-06-30

申请号：US15060807

申请日：2016-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.

公开(公告)号：US09287127B2

公开(公告)日：2016-03-15

申请号：US14181814

申请日：2014-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC: H01L21/302 ,  H01L21/306 ,  B24B9/06 ,  B24B7/22 ,  B24B21/00 ,  H01L21/66 ,  H01L21/02

CPC classification number: H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20 k or finer grit or non-abrasive pads.

Abstract translation: 晶片抛光工艺包括抛光晶片背面的中心区域，抛光晶片背面的周边区域，抛光中心区域，以及抛光周边区域。 该过程可以显着减少划痕相关的晶片断裂，可以校正晶片上的焦点，并可以替代使用化学蚀刻剂的清洗工艺。 抛光和抛光可以包括抛光和抛光斜面区域。 进一步的改进包括用具有柔软背衬的研磨垫，抛光或抛光，具有相对较软的磨料颗粒的垫，抛光或抛光，其中由磨料颗粒制成的研磨垫已被分选并选择成规则形状，冲洗正被抛光的表面 用包含减摩剂的水溶液抛光，并用具有20k或更细砂粒或非研磨垫的研磨垫进行抛光。

公开(公告)号：US10770345B2

公开(公告)日：2020-09-08

申请号：US16112955

申请日：2018-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Chang-Sheng Lin ,  Chien-Chung Huang ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/24

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.